參數(shù)資料
型號: CY23FP12OXIT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時鐘及定時
英文描述: 200-MHz Field Programmable Zero Delay Buffer
中文描述: 23FP SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 5.30 MM, LEAD FREE, SSOP-28
文件頁數(shù): 6/10頁
文件大?。?/td> 201K
代理商: CY23FP12OXIT
CY23FP12
Document #: 38-07246 Rev. *E
Page 6 of 10
Absolute Maximum Conditions
Parameter
V
DD
V
IN
V
IN
LU
I
T
S
T
A
T
A
T
J
Jc
Ja
ESD
h
M
SL
G
ATES
UL–94
FIT
T
PU
Description
Condition
Min.
–0.5
–0.5
–0.5
Max.
7
7
V
DD
+ 0.5
Unit
VDC
VDC
VDC
mA
°C
°C
°C
°C
°C/W
°C/W
V
class
each
class
ppm
ms
Supply Voltage
Input Voltage REF
Input Voltage Except REF
Latch-up Immunity
Temperature, Storage
Temperature, Operating Ambient
Temperature, Operating Ambient
Junction Temperature
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Moisture Sensitivity Level
Total Functional Gate Count
Flammability Rating
Failure in Time
Power-up time for all V
DD
s to reach
minimum specified voltage (power
ramps must be monotonic)
Non-functional
Relative to V
CC
Relative to V
CC
Functional
Non-functional
Commercial Temperature
Industrial Temperature
Industrial Temperature
Functional
Functional
300
–65
0
–40
+125
+70
+85
125
34
86
2000
MSL – 1
21375
V–0
10
Assembled Die
@ 1/8 in.
Manufacturing test
0.05
500
DC Electrical Specifications for CY23FP12SC/I Commercial/Industrial Temperature Devices
Parameter
V
DDC
V
DDA
, V
DDB
Description
Core Supply Voltage
Bank A, Bank B
Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
Typ.
Max.
3.465
3.465
2.625
0.3 × V
DD
Unit
V
V
V
V
V
μ
A
μ
A
V
V
IL
V
IH
I
IL
I
IH
V
OL
Input LOW Voltage
[3]
Input HIGH Voltage
[3]
Input LOW Current
[3]
Input HIGH Current
[3]
Output LOW Voltage
[4]
V
DDA
/V
DDB
= 3.3V, I
OL
= 16 mA (standard drive)
V
DDA
/V
DDB
= 3.3V, I
OL
= 20 mA (high drive)
V
DDA
/V
DDB
= 2.5V, I
OL
= 16 mA (high drive)
Output HIGH
Voltage
[4]
V
DDA
/V
DDB
= 3.3V, I
OH
= –20 mA (high drive)
V
DDA
/V
DDB
= 2.5V, I
OH
= –16 mA (high drive)
Power-down Supply
Current
Supply Current
V
DDA
= V
DDB
= 2.5V, Unloaded outputs @ 166 MHz
V
DDA
= V
DDB
= 2.5V, Loaded outputs @ 166 MHz,
C
L
= 15 pF
V
DDA
= V
DDB
= 3.3V, Unloaded outputs @ 166 MHz
V
DDA
= V
DDB
= 3.3V, Loaded outputs @ 166 MHz,
C
L
= 15 pF
0.7 × V
DD
V
IN
= 0V
V
IN
= V
DD
50.0
50.0
0.5
V
OH
V
DDA
/V
DDB
= 3.3V, I
OH
= –16 mA (standard drive)
V
DD
– 0.5
V
I
DDS
REF = 0 MHz
12
50
μ
A
I
DD
40
65
65.0
100
mA
50
100
80
120
Notes:
3. Applies to both Ref Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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