參數(shù)資料
型號: CY23S09
廠商: Cypress Semiconductor Corp.
英文描述: Low-Cost 3.3V Spread Aware Zero Delay Buffer(低價格3.3V Spread Aware零延遲緩沖器)
中文描述: 低成本3.3V的價差意識到零延遲緩沖器(低價格3.3蔓延意識到零延遲緩沖器)
文件頁數(shù): 5/9頁
文件大小: 207K
代理商: CY23S09
CY23S09
CY23S05
Document #: 38-07296 Rev. *C
Page 5 of 9
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H
Industrial Temperature Devices
[8]
Parameter
t1
Description
Test Conditions
Min.
10
10
40.0
45.0
Typ.
Max.
100
133.33
60.0
55.0
1.50
1.50
250
Unit
MHz
MHz
%
%
ns
ns
ps
Output Frequency
30-pF load
10-pF load
Measured at 1.4V, F
out
= 66.67 MHz
Measured at 1.4V, F
out
<50.0 MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Measured at V
DD
/2
Duty Cycle
[7]
= t
2
÷
t
1
Duty Cycle
[7]
= t
2
÷
t
1
Rise Time
[7]
Fall Time
[7]
Output-to-Output Skew
[7]
Delay, REF Rising Edge to
CLKOUT Rising Edge
[7]
Device-to-Device Skew
[7]
50.0
50.0
t3
t
4
t
5
t
6
0
±350
ps
t
7
Measured at V
DD
/2 on the CLKOUT pins
of devices
Measured between 0.8V and 2.0V using
Test Circuit #2
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock
presented on REF pin
0
700
ps
t
8
Output Slew Rate
[7]
1
V/ns
t
J
t
LOCK
Cycle-to-Cycle Jitter
[7]
PLL Lock Time
[7]
200
ps
1.0
ms
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.8V
2.0V
2.0V
0.8V
t
4
Output-Output Skew
1.4V
1.4V
t
5
OUTPUT
OUTPUT
Input-Output Propagation Delay
V
DD
/2
t
6
INPUT
OUTPUT
V
DD
/2
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