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參數(shù)資料
| 型號(hào)： | CY24212-5 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MediaClock MPEG Clock Generator with VCXO |
| 中文描述： | MediaClock的MPEG時(shí)鐘發(fā)生器，石英振蕩器 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 111K |
| 代理商： | CY24212-5 |
MediaClock
MPEG Clock Generator with VCXO
CY24212
PRELIMINARY
Cypress Semiconductor Corporation
Document #: 38-07402 Rev. *B
3901 North First Street
San Jose, CA 95134
408-943-2600
Revised February 18, 2003
Table 1. CY24212 (-1, -2) Frequency Select Option
Features
Benefits
Integrated phase-locked loop (PLL)
Low jitter, high-accuracy outputs
VCXO with analog adjust
3.3V operation
Highest-performance PLL tailored for multimedia applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Enables application compatibility
Part Number
CY24212-1
CY24212-2
CY24212-3
CY24212-5
Outputs
1
2
2
2
Input Frequency Range
13.5 MHz/27 MHz (selectable)
13.5 MHz/27 MHz (selectable)
27 MHz
27 MHz
Output Frequencies
27 MHz
Two copies of 27 MHz
27 MHz/27.027 MHz (-1 ppm)
27 MHz/27.027 MHz (0 ppm)
FSEL
0
1
Reference
13.5 MHz
27 MHz
CLKA/CLKB
27 MHz
27 MHz
Table 2. CY24212 (-3, -5) Frequency Select Option
FSEL
0
1
Reference
27 MHz
27 MHz
CLKA
27 MHz
27 MHz
CLKB
27 MHz
27.027 MHz
Logic Block Diagram
XOUT
OUTPUT
DIVIDERS
PLL
OSC
VCXO
Q
P
VCO
VDD
VSS
Φ
CLKA (27 MHz)
XIN
FSEL
27 MHz (-2)
27/27.027 MHz (-3)
8-pin SOIC
CY24212-1
Pin Configurations
1
2
3
4
XOUT
XIN
VDD
VCXO
VSS
CLKA 27 MHz
VSS
FSEL
5
6
7
8
8-pin SOIC
CY24212-2
1
2
3
4
XOUT
XIN
VDD
VCXO
VSS
CLKA 27 MHz
CLKB 27 MHz
FSEL
5
6
7
8
8-pin SOIC
CY24212-3,-5
1
2
3
4
XOUT
XIN
VDD
VCXO
VSS
CLKA 27 MHz
CLKB (27/27.027 MHz)
FSEL
5
6
7
8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY24212SC-1T | MediaClock MPEG Clock Generator with VCXO |
| CY24212SC-2 | MediaClock MPEG Clock Generator with VCXO |
| CY24212SC-2T | MediaClock MPEG Clock Generator with VCXO |
| CY24212SC-3 | MediaClock MPEG Clock Generator with VCXO |
| CY24212SC-5 | MediaClock MPEG Clock Generator with VCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY24212KSXC-5 | 功能描述:鎖相環(huán) - PLL MPEG Clock Gen with VCXO RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY24212SC-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock MPEG Clock Generator with VCXO |
| CY24212SC-1T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock⑩ MPEG Clock Generator with VCXO |
| CY24212SC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock⑩ MPEG Clock Generator with VCXO |
| CY24212SC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:MediaClock⑩ MPEG Clock Generator with VCXO |
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