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參數(shù)資料
| 型號： | CY25100 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction |
| 中文描述： | 場和工廠可編程擴(kuò)頻時鐘發(fā)生器減少電磁干擾 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 279K |
| 代理商： | CY25100 |
CY25100
Document #: 38-07499 Rev. *D
Page 4 of 11
Absolute Maximum Rating
Supply Voltage (V
DD
)........................................–0.5 to +7.0V
DC Input Voltage......................................–0.5V to V
DD
+ 0.5
Storage Temperature (Non-condensing).....–55
°
C to +125
°
C
Recommended Crystal Specifications
Junction Temperature................................ –40
°
C to +125
°
C
Data Retention @ Tj = 125
°
C................................> 10 years
Package Power Dissipation......................................350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Parameter
F
NOM
C
LNOM
R
1
R
3
/R
1
Description
Comments
Min. Typ. Max. Unit
8
–
6
–
–
–
3
–
Nominal Crystal Frequency
Nominal Load Capacitance
Equivalent Series Resistance (ESR)
Ratio of Third Overtone Mode ESR to
Fundamental Mode ESR
Crystal Drive Level
Parallel resonance, fundamental mode, AT cut
Internal load caps
Fundamental mode
Ratio used because typical R
1
values are much
less than the maximum spec
No external series resistor assumed
30
30
25
–
MHz
pF
–
DL
–
0.5
2
mW
Operating Conditions
Parameter
Description
Min.
3.13
0
–40
–
8
Typ.
3.30
–
–
–
–
Max.
3.45
70
85
15
30
Unit
V
°C
°C
pF
MHz
V
DD
T
A
Supply Voltage
Ambient Commercial Temperature
Ambient Industrial Temperature
Max. Load Capacitance @ pin 6 and pin 7
External Reference Crystal
(Fundamental tuned crystals only)
External Reference Clock
SSCLK output frequency, C
LOAD
= 15 pF
REFCLK output frequency, C
LOAD
= 15 pF
Spread Spectrum Modulation Frequency
Power-up time for all VDDs to reach minimum spec-
ified voltage (power ramp must be monotonic)
C
LOAD
F
ref
8
3
8
–
–
–
166
200
166
33.0
500
MHz
MHz
MHz
kHz
ms
F
SSCLK
F
REFCLK
F
MOD
T
PU
30.0
0.05
31.5
–
DC Electrical Characteristics
Parameter
Description
Condition
Min.
10
10
0.7V
DD
–
–
Typ.
12
12
–
–
–
Max.
Unit
mA
mA
V
V
μ
A
I
OH
I
OL
V
IH
V
IL
I
IH
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input High Current, PD#/OE and
SSON# pins
Input Low Current, PD#/OE and
SSON# pins
Output Leakage Current
Programmable Capacitance at pin
2 and pin 3
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
V
in
= V
DD
V
DD
0.3V
DD
10
I
IL
V
in
= V
SS
–
–
10
μ
A
I
OZ
C
XIN
or C
XOUT[1]
Three-state output, PD#/OE = 0
Capacitance at minimum setting
Capacitance at maximum setting
Input pins excluding XIN and XOUT
–10
–
–
–
10
–
–
7
μ
A
pF
pF
pF
12
60
5
C
IN[1]
Input Capacitance at pin 4 and pin
8
Supply Current
I
VDD
V
= 3.45V, Fin = 30 MHz,
REFCLK = 30 MHz, SSCLK = 66 MHz,
C
LOAD
= 15 pF, PD#/OE = SSON# = V
DD
V
= 3.45V, Device powered down with
PD# = 0V (driven reference pulled down)
–
25
35
mA
I
DDS
Standby current
–
15
30
μ
A
Notes:
1. Guaranteed by characterization, not 100% tested.
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