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參數(shù)資料
| 型號： | CY28326 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FTG for VIA PT880 Serial Chipset |
| 中文描述： | FTG的威盛PT880系列芯片組 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 288K |
| 代理商： | CY28326 |
CY28326
Document #: 38-07616 Rev. *A
Page 4 of 23
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power down operation.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write and block read operation from any external I
2
C
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For byte write and byte read opera-
tions, the system controller can access individual indexed
bytes. The offset of the indexed byte is encoded in the
command code, as described in
Table 4
. The block write and
block read protocol is outlined in
Table 5
while
Table 6
outlines
the corresponding byte write and byte read protocol.The slave
receiver address is 11010010 (D2h).
Table 2. Mode Ratio Setting
Power-up Condition
Pin I/O Setting
Mode
0
0
1
1
RatioSel
x
x
0
1
Pin 19
PCI_STP#
PCI_STP#
Ratio0
PCI5
Pin 20
CPU_STP#
CPU_STP#
Ratio1
PCI6
Table 3. Ratio mapping Table
Power-up Frequency value
CPU
100
133
200
166
FS[1:0]
Ratio pin mapping
Pin 20
0
0
1
1
AGP
66.6
66.6
66.6
66.6
FS1
0
0
1
1
FS0
0
1
0
1
Pin 19
0
1
0
1
Table 4. Command Code Definition
Bit
7
Description
0 = Block read or block write operation
1 = Byte read or byte write operation
Device selection bits. Set = 00
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
(6:5)
(4:0)
Table 5. Block Read and Block Write protocol
Block Write Protocol
Description
Block Read Protocol
Description
Bit
1
8:2
9
10
18:11
19
27:20
Bit
1
8:2
9
10
18:11
19
20
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Repeat start
28
27:21
28
29
37:30
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
36:29
37
45:38
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|---|---|
| CY28326OC | FTG for VIA PT880 Serial Chipset |
| CY28326OCT | FTG for VIA PT880 Serial Chipset |
| CY28326OXC | Single Pole Normally Open: 1-Form-A |
| CY28326OXCT | Single Pole Normally Open: 1-Form-A |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28326OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326OXC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28326OXCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326SPC | 制造商:Cypress Semiconductor 功能描述: |
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