- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9018 > CY28346ZI-2T (Silicon Laboratories Inc)IC CLOCK DIFF OUT CK408 56TSSOP PDF資料下載
參數(shù)資料
| 型號： | CY28346ZI-2T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 19/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIFF OUT CK408 56TSSOP |
| 標準包裝： | 2,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
CY28346-2
........................ Document #: 38-07509 Rev. *B Page 9 of 19
CPU_STP# Clarification
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
CPU_STP# Assertion
When CPU_STP# pin is asserted, all CPUT/C outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
falling CPUT/C clock edges. The final state of the stopped
CPU signals is CPUT = HIGH and CPU0C = LOW. There is no
change to the output drive current values during the stopped
state. The CPUT is driven HIGH with a current value equal to
(Mult 0 ‘select’) x (Iref), and the CPUC signal will not be driven.
Due to external pull-down circuitry CPUC will be LOW during
this stopped state.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all
CPUT/C outputs that were stopped to resume normal
operation in a synchronous manner. Synchronous manner
meaning that no short or stretched clock pulses will be
produces when the clock resumes. The maximum latency
from the deassertion to active outputs is no more than two
CPUC clock cycles.
CPU _ ST P#
CPUT
CPU C
CPUT
CPU C
Figure 4. CPU_STP# Assertion Waveforms
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 5. CPU_STP# Deassertion Waveforms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS87946AYI-147LFT | IC CLOCK GENERATOR 32-LQFP |
| VI-B31-MV-F3 | CONVERTER MOD DC/DC 12V 150W |
| CY28419OXCT | IC CLOCK SRC CK409B 56SSOP |
| MK1725GILF | IC CLK GEN SPRD SPECTRUM 16TSSOP |
| MK1714-02RILF | IC CLK MULT SPRD SPECTRUM 20QSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28346ZXC | 功能描述:時鐘合成器/抖動清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28346ZXC-2 | 功能描述:時鐘合成器/抖動清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28346ZXC-2T | 功能描述:時鐘合成器/抖動清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28346ZXCT | 功能描述:時鐘合成器/抖動清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28347 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。