- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9596 > CY28410ZXC (Silicon Laboratories Inc)IC CLOCK CK410GRANTSDALE 56TSSOP PDF資料下載
參數(shù)資料
| 型號： | CY28410ZXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK410GRANTSDALE 56TSSOP |
| 標準包裝： | 35 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:19 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 266MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | SLCY28410ZXC |
CY28410
........................Document #: 38-07593 Rev. *C Page 8 of 17
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tance loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| D38999/24WJ4SA | CONN RCPT 56POS JAM NUT W/SCKT |
| ISL81487EIB-T | IC TXRX RS485/422 5V HS 8-SOIC |
| D38999/26SD18PN | CONN PLUG 18POS STRAIGHT W/PINS |
| VI-22L-MY-S | CONVERTER MOD DC/DC 28V 50W |
| VE-232-MX-F1 | CONVERTER MOD DC/DC 15V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28410ZXC-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410ZXC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410ZXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28411 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28411-1 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Alviso Chipset |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。