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參數(shù)資料
| 型號： | CY29962 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer |
| 中文描述： | 2.5V/3.3V的，150兆赫多輸出零延遲緩沖器 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 91K |
| 代理商： | CY29962 |
CY29962
Document #: 38-07364 Rev. *B
Page 3 of 7
Description
The CY29962 has an integrated PLL that provides low skew
and low jitter clock outputs for high-performance micropro-
cessors. Three independent banks of seven outputs as well as
an independent PLL feedback output, FB_OUT, provide
exceptional flexibility for possible output configurations. The
PLL is ensured stable operation given that the VCO is
configured to run between 200 MHz to 400 MHz. This allows
a wide range of output frequencies up to 150 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL select inputs (see
Table 1
).
The VCO frequency is then divided down to provide the
required output frequencies.
Zero Delay Buffer
When used as a zero delay buffer, the CY29962 will likely be
in a nested clock tree application. For these applications the
CY29962 offers a low-voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far superior
skew performance. The CY29962 can then lock onto the
LVPECL reference and translate with near zero delay to
low-skew outputs.
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge,
thus producing a near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs. Because the static
phase offset is a function of the reference clock, the Tpd of the
CY29962 is a function of the configuration used.
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| CY2997-000 | 制造商:TE Connectivity 功能描述:CCK-ELKSL-1/3-C |
| CY29972 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 125-MHz Multi-Output Zero Delay Buffer |
| CY29972_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 125-MHz Multi-Output Zero Delay Buffer |
| CY29972_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V, 125-MHz Multi-Output Zero Delay Buffer Output frequency up to 125 MHz |
| CY29972_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3 V, 125-MHz Multi-Output Zero Delay Buffer |
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