- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9640 > CY2SSTV857ZI-27T (Silicon Laboratories Inc)IC CLK DDR266/333BUF1:10 48TSSOP PDF資料下載
參數(shù)資料
| 型號： | CY2SSTV857ZI-27T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DDR266/333BUF1:10 48TSSOP |
| 標準包裝： | 2,000 |
| 系列： | * |
| 類型： | * |
| PLL： | * |
| 主要目的： | * |
| 輸入： | * |
| 輸出： | * |
| 電路數(shù)： | * |
| 比率 - 輸入:輸出： | * |
| 差分 - 輸入:輸出： | * |
| 頻率 - 最大： | * |
| 電源電壓： | * |
| 工作溫度： | * |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
CY2SSTV857
.......................... Document #: 38-07464 Rev. *F Page 2 of 8
Zero-delay Buffer
When used as a zero-delay buffer the CY2SSTV857-27 will
likely be in a nested clock tree application. For these applica-
tions the CY2SSTV857-27 offers a differential clock input pair
as a PLL reference. The CY2SSTV857-27 then can lock onto
the reference and translate with near-zero delay to low-skew
outputs. For normal operation, the external feedback input,
FBIN, is connected to the feedback output, FBOUT. By
connecting the feedback output to the feedback input the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing a near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between the inputs and outputs.
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Power Management
Output enable/disable control of the CY2SSTV857-27 allows
the user to implement power management schemes into the
design. Outputs are three-stated/disabled when PD# is
asserted low (see Table 1).
Note:
1. A bypass capacitor (0.1
F) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Pin Description
Pin Number
Pin Name
I/O[1]
Pin Description
Electrical
Characteristics
13, 14
CLK, CLK#
I
Differential Clock Input.
LV Differential Input
35
FBIN#
I
Feedback Clock Input. Connect to FBOUT# for accessing the
PLL.
Differential Input
36
FBIN
I
Feedback Clock Input. Connect to FBOUT for accessing the
PLL.
3, 5, 10, 20, 22
Y(0:4)
O
Clock Outputs
Differential Outputs
2, 6, 9, 19, 23
Y#(0:4)
O
Clock Outputs
27, 29, 39, 44, 46
Y(9:5)
O
Clock Outputs
Differential Outputs
26, 30, 40, 43, 47
Y#(9:5)
O
Clock Outputs
32
FBOUT
O
Feedback Clock Output. Connect to FBIN for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
Differential Outputs
33
FBOUT#
O
Feedback Clock Output. Connect to FBIN# for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
37
PD#
I
Power Down# Input. When PD# is set HIGH, all Q and Q#
outputs are enabled and switch at the same frequency as CLK.
When set LOW, all Q and Q# outputs are disabled Hi-Z and the
PLL is powered down.
4, 11,12,15, 21, 28,
34, 38, 45
VDDQ
2.5V Power Supply for Output Clock Buffers.2.5V Nominal
16
AVDD
2.5V Power Supply for PLL. When VDDA is at GND, PLL is
bypassed and CLK is buffered directly to the device outputs.
During disable (PD# = 0), the PLL is powered down.
2.5V Nominal
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
VSS
Common Ground
0.0V Ground
17
AVSS
Analog Ground
0.0V Analog
Ground
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V48B24H250BF3 | CONVERTER MOD DC/DC 24V 250W |
| VI-B4D-MW-F3 | CONVERTER MOD DC/DC 85V 100W |
| VI-B44-MW-F4 | CONVERTER MOD DC/DC 48V 100W |
| D38999/20SD19PA | CONN RCPT 19POS WALL MNT W/PINS |
| SL28EB717ALIT | IC CLK CK505 TNLCRK/TOPCLF 48QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2SSTV857ZI-32 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver DDR400/PC3200-Compliant |
| CY2SSTV857ZI-32T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Differential Clock Buffer/Driver DDR400/PC3200-Compliant |
| CY2SSTV857ZXC-27 | 功能描述:時鐘緩沖器 2.5V 60-200MHz 1:10 Diff DDR266/333 B/D RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2SSTV857ZXC-27T | 功能描述:時鐘緩沖器 2.5V 60-200MHz 1:10 Diff DDR266/333 B/D RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2SSTV857ZXC-32 | 功能描述:時鐘緩沖器 2.5V 60-200MHz 1:10 Diff DDR266/333 B/D RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。