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參數(shù)資料
| 型號： | CY37064VP100-100BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 5V, 3.3V, ISR⑩ High-Performance CPLDs |
| 中文描述： | EE PLD, 12 ns, PBGA100 |
| 封裝： | 11 X 11 MM, 1.4 MM HEIGHT, 1 MM PITCH, FBGA-100 |
| 文件頁數(shù)： | 5/62頁 |
| 文件大?。?/td> | 1782K |
| 代理商： | CY37064VP100-100BBI |
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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 5 of 62
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2
illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many appli-
cations.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-
interface applications. Bus-hold additionally allows unused
device pins to remain unconnected on the board, which is
particularly useful during prototyping as designers can route
new signals to the device without cutting trace connections to
V
CC
or GND. For more information, see the application note
“Understanding Bus-Hold — A Feature of Cypress CPLDs.”
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY37064VP100-143AC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| CY37064VP100-143AXC | 功能描述:CPLD - 復雜可編程邏輯器件 64 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| CY37064VP100-143BBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs |
| CY37064VP44-100AC | 制造商:Cypress Semiconductor 功能描述:EE PLD, 12 ns, PQFP44 |
| CY37064VP44-100ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs |
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