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參數(shù)資料
| 型號： | CY37128VP208-200UXC |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | BATT SEALED LEAD ACID 12V 20AH |
| 中文描述： | 為5V，3.3V，ISRTM高性能的CPLD |
| 文件頁數(shù)： | 45/64頁 |
| 文件大?。?/td> | 1798K |
| 代理商： | CY37128VP208-200UXC |
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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 5 of 64
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2 illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many appli-
cations.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in
bus-interface
applications.
Bus-hold
additionally
allows
unused device pins to remain unconnected on the board,
which is particularly useful during prototyping as designers can
route new signals to the device without cutting trace connec-
tions to VCC or GND. For more information, see the application
note Understanding Bus-Hold—A Feature of Cypress CPLDs.
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
C2 C3
DECODE
C2 C3
DECODE
0
1
2
3
O
C6 C5
“0”
“1”
0
1
O
D/T/L
Q
R
P
0
1
2
3
O
C0
0
1
O
C4
FEEDBACK TO PIM
BLOCK RESET
0
16
TERMS
I/O MACROCELL
I/O CELL
FROM PTM
0
1
O
D/T/L
Q
R
P
FROM PTM
1
O
C7
FEEDBACK TO PIM
BURIED MACROCELL
0
ASYNCHRONOUS
PRODUCT
0
16
TERMS
PRODUCT
C1
4
0
1
2
3
Q
4
C24
C0 C1 C24
C25
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
BLOCK PRESET
ASYNCHRONOUS
FAST
SLOW
C26
SLEW
0
1
0
1
0
1
0
1
OE0 OE1
Figure 2. I/O and Buried Macrocells
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY37128VP208-200YXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs |
| CY37128VP208-66AXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs |
| CY37128VP208-66BAXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs |
| CY37128VP208-66BGXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs |
| CY37128VP208-66JXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs |
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