參數(shù)資料
型號： CY37128VP44-100YXC
廠商： Cypress Semiconductor Corp.
英文描述： 5V, 3.3V, ISRTM High-Performance CPLDs
中文描述： 為5V，3.3V，ISRTM高性能的CPLD
文件頁數(shù)： 17/64頁
文件大小： 1792K
代理商： CY37128VP44-100YXC
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 17 of 64
Parameter
[11]
t
ER(–)
V
X
1.5V
Output Waveform—Measurement Level
t
ER(+)
2.6V
t
EA(+)
1.5V
t
EA(–)
V
the
(d) Test Waveforms
V
OH
V
X
0.5V
V
OL
V
X
0.5V
V
X
V
OH
0.5V
V
X
V
OL
0.5V
Switching Characteristics
Over the Operating Range
[12]
Parameter
Combinatorial Mode Parameters
t
PD[13, 14, 15]
t
PDL[13, 14, 15]
t
PDLL[13, 14, 15]
t
EA[13, 14, 15]
t
ER[11, 13]
Input Register Parameters
t
WL
t
WH
t
IS
t
IH
t
ICO[13, 14, 15]
t
ICOL[13, 14, 15]
Synchronous Clocking Parameters
t
CO[14, 15]
t
S[13]
t
H
t
CO2[13, 14, 15]
Description
Unit
Input to Combinatorial Output
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
Input to Output Disable
ns
ns
ns
ns
ns
Clock or Latch Enable Input LOW Time
[8]
Clock or Latch Enable Input HIGH Time
[8]
Input Register or Latch Set-up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ns
ns
ns
ns
ns
ns
Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output
Set-Up Time from Input to Sync. Clk (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Register or Latch Data Hold Time
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
0
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
0
,
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
ns
ns
ns
ns
t
SCS[13]
ns
t
SL[13]
ns
t
HL
ns
Notes:
11. t
measured with 5-pF AC Test Load and t
measured with 35-pF AC Test Load.
12.All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13.Logic Blocks operating in Low-Power Mode, add t
to this spec.
14.Outputs using Slow Output Slew Rate, add t
SLEW
to this spec.
15.When V
CCO
= 3.3V, add t
3.3IO
to this spec.
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