參數(shù)資料
型號(hào): CY37128VP48-83NTXC
廠商: Cypress Semiconductor Corp.
英文描述: 5V, 3.3V, ISRTM High-Performance CPLDs
中文描述: 為5V,3.3V,ISRTM高性能的CPLD
文件頁(yè)數(shù): 17/64頁(yè)
文件大?。?/td> 1792K
代理商: CY37128VP48-83NTXC
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 17 of 64
Parameter
[11]
t
ER(–)
V
X
1.5V
Output Waveform—Measurement Level
t
ER(+)
2.6V
t
EA(+)
1.5V
t
EA(–)
V
the
(d) Test Waveforms
V
OH
V
X
0.5V
V
OL
V
X
0.5V
V
X
V
OH
0.5V
V
X
V
OL
0.5V
Switching Characteristics
Over the Operating Range
[12]
Parameter
Combinatorial Mode Parameters
t
PD[13, 14, 15]
t
PDL[13, 14, 15]
t
PDLL[13, 14, 15]
t
EA[13, 14, 15]
t
ER[11, 13]
Input Register Parameters
t
WL
t
WH
t
IS
t
IH
t
ICO[13, 14, 15]
t
ICOL[13, 14, 15]
Synchronous Clocking Parameters
t
CO[14, 15]
t
S[13]
t
H
t
CO2[13, 14, 15]
Description
Unit
Input to Combinatorial Output
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
Input to Output Disable
ns
ns
ns
ns
ns
Clock or Latch Enable Input LOW Time
[8]
Clock or Latch Enable Input HIGH Time
[8]
Input Register or Latch Set-up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ns
ns
ns
ns
ns
ns
Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output
Set-Up Time from Input to Sync. Clk (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Register or Latch Data Hold Time
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
0
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
0
,
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
ns
ns
ns
ns
t
SCS[13]
ns
t
SL[13]
ns
t
HL
ns
Notes:
11. t
measured with 5-pF AC Test Load and t
measured with 35-pF AC Test Load.
12.All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13.Logic Blocks operating in Low-Power Mode, add t
to this spec.
14.Outputs using Slow Output Slew Rate, add t
SLEW
to this spec.
15.When V
CCO
= 3.3V, add t
3.3IO
to this spec.
相關(guān)PDF資料
PDF描述
CY37128VP48-83NXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-83UXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP84-100NTXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP84-100NXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP84-100UXC 5V, 3.3V, ISRTM High-Performance CPLDs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY37128VP48-83NXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-83UXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP48-83YXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:5V, 3.3V, ISRTM High-Performance CPLDs
CY3716 功能描述:IC 與器件插座 Socket Adapter RoHS:否 制造商:Molex 產(chǎn)品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點(diǎn)數(shù)量:2011 觸點(diǎn)電鍍:Gold 安裝風(fēng)格:SMD/SMT 端接類型:Solder 插座/封裝類型:LGA 2011 工作溫度范圍:- 40 C to + 100 C
CY37192P160-125AC 功能描述:IC CPLD 192 MACROCELL 160LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:40 系列:ispMACH® 4000C 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):5.0ns 電壓電源 - 內(nèi)部:1.65 V ~ 1.95 V 邏輯元件/邏輯塊數(shù)目:32 宏單元數(shù):512 門數(shù):- 輸入/輸出數(shù):128 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:176-LQFP 供應(yīng)商設(shè)備封裝:176-TQFP(24x24) 包裝:托盤