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參數(shù)資料
| 型號(hào)： | CY37256P160-83AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 5V, 3.3V, ISRTM High-Performance CPLDs |
| 中文描述： | EE PLD, 15 ns, PQFP160 |
| 封裝： | 24 X 24 MM, 1.4 MM HEIGHT, PLASTIC, TQFP-160 |
| 文件頁數(shù)： | 5/64頁 |
| 文件大?。?/td> | 1798K |
| 代理商： | CY37256P160-83AI |
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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 5 of 64
The buried macrocell also supports input register capability.
The buried macrocell can be configured to act as an input
register (D-type or latch) whose input comes from the I/O pin
associated with the neighboring macrocell. The output of all
buried macrocells is sent directly to the PIM regardless of its
configuration.
I/O Macrocell
Figure 2
illustrates the architecture of the I/O macrocell. The
I/O macrocell supports the same functions as the buried
macrocell with the addition of I/O capability. At the output of the
macrocell, a polarity control mux is available to select active
LOW or active HIGH signals. This has the added advantage
of allowing significant logic reduction to occur in many appli-
cations.
The Ultra37000 macrocell features a feedback path to the PIM
separate from the I/O pin input path. This means that if the
macrocell is buried (fed back internally only), the associated
I/O pin can still be used as an input.
Bus Hold Capabilities on all I/Os
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in
bus-interface applications. Bus-hold additionally allows
unused device pins to remain unconnected on the board,
which is particularly useful during prototyping as designers can
route new signals to the device without cutting trace connec-
tions to V
CC
or GND. For more information, see the application
note
Understanding Bus-Hold—A Feature of Cypress CPLDs
.
Programmable Slew Rate Control
Each output has a programmable configuration bit, which sets
the output slew rate to fast or slow. For designs concerned with
meeting FCC emissions standards the slow edge provides for
lower system noise. For designs requiring very high perfor-
mance the fast edge rate provides maximum system perfor-
mance.
C2
C3
DECODE
C2
C3
DECODE
0
1
2
3
O
C6 C5
“0”
“1”
0
1
O
D/T/L
Q
R
P
0
1
2
3
4
O
C0
0
1
O
C4
FEEDBACK TO PIM
FEEDBACK TO PIM
BLOCK RESET
ASYNCHRONOUS
0
16
TERMS
I/O MACROCELL
I/O CELL
FROM PTM
0
1
O
D/T/L
Q
R
P
FROM PTM
0
16
PRODUCT
1
O
C7
FEEDBACK TO PIM
BURIED MACROCELL
0
ASYNCHRONOUS
PRODUCT
TERMS
C1
0
1
2
3
4
Q
C24
C0 C1C24
C25
C25
4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)
1 ASYNCHRONOUS CLOCK(PTCLK)
Figure 2. I/O and Buried Macrocells
BLOCK PRESET
FAST
SLOW
C26
SLEW
0
1
0
1
0
1
0
1
OE0 OE1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY37256P160-83AXC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 256 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| CY37256P160-83AXI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 256 Macrocell 5V IND RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| CY37256P160-83UM | 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells CMOS Technology 5V 160-Pin CQFP |
| CY37256P208-125NC | 制造商:Cypress Semiconductor 功能描述: |
| CY37256P208-125NI | 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells 125MHz 5V 208-Pin PQFP |
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