參數(shù)資料
型號(hào)： CY37256VP208-66NC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： 5V, 3.3V, ISR⑩ High-Performance CPLDs
中文描述： EE PLD, 20 ns, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 8/62頁(yè)
文件大?。?/td> 1782K
代理商： CY37256VP208-66NC
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 8 of 62
IEEE 1149.1-compliant JTAG
The Ultra37000 family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR.
Boundary Scan
The Ultra37000 family supports Bypass, Sample/Preload,
Extest, Idcode, and Usercode boundary scan instructions. The
JTAG interface is shown in
Figure 6
.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Ultra37000 family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
Development Software Support
Warp
Warp is a state-of-the-art compiler and complete CPLD design
tool. For design entry, Warp provides an IEEE-STD-1076/1164
VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a
graphical finite state machine editor. It provides optimized
synthesis and fitting by replacing basic circuits with ones pre-
optimized for the target device, by implementing logic in
unused memory and by perfect communication between fitting
and synthesis. To facilitate design and debugging, Warp
provides graphical timing simulation and analysis.
Warp
Professional
Warp
Professional contains several additional features. It
provides an extra method of design entry with its graphical
block diagram editor. It allows up to 5 ms timing simulation
instead of only 2 ms. It allows comparison of waveforms before
and after design changes.
Warp
Enterprise
Warp
Enterprise provides even more features. It provides
unlimited timing simulation and source-level behavioral
simulation as well as a debugger. It has the ability to generate
graphical HDL blocks from HDL text. It can even generate
testbenches.
Warp
is available for PC and UNIX platforms. Some features
are not available in the UNIX version. For further information
see the
Warp
for PC
, Warp
for UNIX,
Warp
Professional and
Warp
Enterprise data sheets on Cypress’s web site
(www.cypress.com).
Third-Party Software
Although
Warp
is a complete CPLD development tool on its
own, it interfaces with nearly every third party EDA tool. All
major third-party software vendors provide support for the
Ultra37000 family of devices. Refer to the third-party software
data sheet or contact your local sales office for a list of
currently supported third-party vendors.
Programming
There are four programming options available for Ultra37000
devices. The first method is to use a PC with the 37000
UltraISR programming cable and software. With this method,
the ISR pins of the Ultra37000 devices are routed to a
connector at the edge of the printed circuit board. The 37000
UltraISR programming cable is then connected between the
parallel port of the PC and this connector. A simple configu-
ration file instructs the ISR software of the programming
operations to be performed on each of the Ultra37000 devices
in the system. The ISR software then automatically completes
all of the necessary data manipulations required to accomplish
the programming, reading, verifying, and other ISR functions.
For more information on the Cypress ISR Interface, see the
ISR Programming Kit data sheet (CY3700i).
The second method for programming Ultra37000 devices is on
automatic test equipment (ATE). This is accomplished through
a file created by the ISR software. Check the Cypress website
for the latest ISR software download information.
The third programming option for Ultra37000 devices is to
utilize the embedded controller or processor that already
exists in the system. The Ultra37000 ISR software assists in
this method by converting the device JEDEC maps into the
ISR serial stream that contains the ISR instruction information
and the addresses and data of locations to be programmed.
The embedded controller then simply directs this ISR stream
to the chain of Ultra37000 devices to complete the desired
reconfiguring or diagnostic operations. Contact your local
sales office for information on availability of this option.
The fourth method for programming Ultra37000 devices is to
use the same programmer that is currently being used to
program F
LASH
370i devices.
For all pinout, electrical, and timing requirements, refer to
device data sheets. For ISR cable and software specifications,
refer to the UltraISR kit data sheet (CY3700i).
Third-Party Programmers
As with development software, Cypress support is available
on a wide variety of third-party programmers. All major third-
party programmers (including BP Micro, Data I/O, and SMS)
support the Ultra37000 family.
Figure 6. JTAG Interface
Instruction Register
Boundary Scan
idcode
Usercode
ISR Prog.
Bypass Reg.
Data Registers
JTAG
TAP
CONTROLLER
TDO
TDI
TMS
TCK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY37256VP208-66NI 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells 66MHz 3.3V 208-Pin PQFP
CY37256VP208-66NXC 功能描述:IC CPLD 256 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤
CY37256VP208-66NXI 功能描述:IC CPLD 256 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤
CY37256VP256-100BBC 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY37256VP256-100BGC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 256 Macrocell 5V COM RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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