參數(shù)資料
型號(hào): CY3732VP84-154NXC
廠商: Cypress Semiconductor Corp.
英文描述: 5V, 3.3V, ISRTM High-Performance CPLDs
中文描述: 為5V,3.3V,ISRTM高性能的CPLD
文件頁數(shù): 17/64頁
文件大?。?/td> 1798K
代理商: CY3732VP84-154NXC
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 17 of 64
Parameter
[11]
t
ER(–)
V
X
1.5V
Output Waveform—Measurement Level
t
ER(+)
2.6V
t
EA(+)
1.5V
t
EA(–)
V
the
(d) Test Waveforms
V
OH
V
X
0.5V
V
OL
V
X
0.5V
V
X
V
OH
0.5V
V
X
V
OL
0.5V
Switching Characteristics
Over the Operating Range
[12]
Parameter
Combinatorial Mode Parameters
t
PD[13, 14, 15]
t
PDL[13, 14, 15]
t
PDLL[13, 14, 15]
t
EA[13, 14, 15]
t
ER[11, 13]
Input Register Parameters
t
WL
t
WH
t
IS
t
IH
t
ICO[13, 14, 15]
t
ICOL[13, 14, 15]
Synchronous Clocking Parameters
t
CO[14, 15]
t
S[13]
t
H
t
CO2[13, 14, 15]
Description
Unit
Input to Combinatorial Output
Input to Output Through Transparent Input or Output Latch
Input to Output Through Transparent Input and Output Latches
Input to Output Enable
Input to Output Disable
ns
ns
ns
ns
ns
Clock or Latch Enable Input LOW Time
[8]
Clock or Latch Enable Input HIGH Time
[8]
Input Register or Latch Set-up Time
Input Register or Latch Hold Time
Input Register Clock or Latch Enable to Combinatorial Output
Input Register Clock or Latch Enable to Output Through Transparent Output Latch
ns
ns
ns
ns
ns
ns
Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output
Set-Up Time from Input to Sync. Clk (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Register or Latch Data Hold Time
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Combinatorial Output
Delay (Through Logic Array)
Output Synchronous Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable to Output Synchronous
Clock (CLK
0
, CLK
1
, CLK
2
, or CLK
3
) or Latch Enable (Through Logic Array)
Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK
0
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK
0
,
CLK
1
, CLK
2
, or CLK
3
) or Latch Enable
ns
ns
ns
ns
t
SCS[13]
ns
t
SL[13]
ns
t
HL
ns
Notes:
11. t
measured with 5-pF AC Test Load and t
measured with 35-pF AC Test Load.
12.All AC parameters are measured with two outputs switching and 35-pF AC Test Load.
13.Logic Blocks operating in Low-Power Mode, add t
to this spec.
14.Outputs using Slow Output Slew Rate, add t
SLEW
to this spec.
15.When V
CCO
= 3.3V, add t
3.3IO
to this spec.
相關(guān)PDF資料
PDF描述
CY3764VP84-154NXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37128VP84-154NXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37256VP84-154NXC 5V, 3.3V, ISRTM High-Performance CPLDs
CY37384VP84-154NXC 16K ROM & 512 EEPROM
CY3732VP100-154NXC 5V, 3.3V, ISRTM High-Performance CPLDs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY37512P208-100NI 制造商:Cypress Semiconductor 功能描述:
CY37512P208-100NXI 功能描述:IC CPLD 512 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP(28x28) 包裝:托盤
CY37512P208-125NC 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 125MHz 5V 208-Pin PQFP 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 125MHz CMOS Technology 5V 208-Pin PQFP
CY37512P208-125NXC 功能描述:IC CPLD 512 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD(復(fù)雜可編程邏輯器件) 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP(28x28) 包裝:托盤
CY37512P208-83NC 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 15K Gates 512 Macro Cells 83MHz 5V 208-Pin PQFP