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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 27 of 64
CY37384
CY37512
Typical 5.0V Power Consumption
(continued)
0
50
100
150
200
250
300
350
400
450
500
0
20
40
60
80
100
120
140
160
Frequency (MHz)
I
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5.0V, T
A
= Room Temperature
0
100
200
300
400
500
600
0
20
40
60
80
100
120
140
160
Frequency (MHz)
I
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 5.0V, T
A
= Room Temperature