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參數(shù)資料
| 型號： | CY38030V144-66BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 18.9 ns, PBGA144 |
| 封裝： | FBGA-144 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 929K |
| 代理商： | CY38030V144-66BBI |
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PRELIMINARY
Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. **
Page 7 of 32
Embedded Memory
The Quantum38K architecture includes an embedded channel
memory block at each crossing point of horizontal and vertical
routing channels. The channel memory is a 4096-bit memory
block that can be configured as asynchronous or synchronous
Single-Port RAM, Dual-Port RAM, or Read-Only memory
(ROM). The memory organization is configurable as 4Kx1,
2Kx2,1Kx4 or 512x8.
Data, address, and control inputs to the channel memory are
driven from horizontal and vertical routing channels. All data
logic outputs drive dedicated tracks in the horizontal and ver-
tical routing channels. The clocks for the channel memory
block are selected from four global clocks and pin inputs from
the horizontal and vertical channels. The clock muxes also
include a polarity mux for each clock so that the user can
choose an inverted clock.
Dual-Port (Channel Memory) Configuration
Each port has distinct address inputs, as well as separate data
and control inputs that can be accessed simultaneously. The
inputs to the Dual-Port memory are driven from the horizontal
and vertical routing channels. The data outputs drive dedicat-
ed tracks in the routing channels. The interface to the routing
is such that Port A of the Dual-Port interfaces primarily with the
horizontal routing channel and Port B interfaces primarily with
the vertical routing channel.
.
The clocks for each port of the Dual-Port configuration are
selected from four global clocks and two local clocks. One lo-
cal clock is sourced from the horizontal channel and the other
from the vertical channel. The data outputs of the dual-port
memory can also be registered. Clocks for the output registers
are also selected from four global clocks and two local clocks.
One clock polarity mux per port allows the use of true or com-
plement polarity for input and output clocking purposes.
Arbitration
The Dual-Port configuration of the Channel Memory Block pro-
vides arbitration when both ports access the same address at
the same time. Depending on the memory operations being
attempted, one port always gets priority. See Table 1 for details
on which port gets priority for read and write operations. An
active-LOW ‘Address Match’ signal is generated when an ad-
dress collision occurs.
Channel Memory Initialization
The channel memory powers up in an undefined state, but is
set to a user-defined known state during configuration. To fa-
cilitate the use of look-up-table (LUT) logic and ROM applica-
tions, the channel memory blocks can be initialized with a giv-
en set of data when the device is configured at power up. For
LUT and ROM applications, the user cannot write to memory
blocks.
Table 1. Arbitration Result: Address Match Signal
Becomes Active
Port A
Port B
Result of
Arbitration
Comment
Read
No arbitration
required
Both ports read at the
same time
Write
Read
Port A gets
priority
If Port B requests first
then it will read the cur-
rent data. The output will
then change to the newly
written data by Port A
Read
Write
Port B gets
priority
If Port A requests first
then it will read the cur-
rent data. The output will
then change to the newly
written data by Port B
Write
Port A gets
priority
Port B is blocked until
Port A is finished writing
Figure 5. Block Diagram of Channel Memory Block
4096-bit Dual Port
Array
Configurable as
Async/Sync Dual Port
Configurable as
4Kx1, 2Kx2, 1Kx4 and
512x8 block sizes
Horizontal Channel
All channel memory
inputs are driven from
the routing channels
All channel memory outputs
drive dedicated tracks in the
routing channels
GCLK[3:0]
Global Clock
Signals
Ver
tic
al
C
hannel
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY38050V208-125NTC | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk |
| CY38050V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk |
| CY38050V208-83NTC | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk |
| CY38050V208-83NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk |
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