參數(shù)資料
型號： CY39030Z144-222BBC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 7 ns, PBGA144
封裝： 1 MM PITCH, FBGA-144
文件頁數(shù)： 10/57頁
文件大?。?/td> 1166K
代理商： CY39030Z144-222BBC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 18 of 57
Power-up Sequence Requirements
Upon power-up, all the outputs remain three-stated until all
the VCC pins have powered-up to the nominal voltage and
the part has completed configuration.
The part will not start configuration until VCC, VCCIO,
VCCJTAG, VCCCNFG, VCCPLL and VCCPRG have reached
nominal voltage.
VCC pins can be powered up in any order. This includes
VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCCPRG.
All VCCIOs on a bank should be tied to the same potential
and powered up together.
All VCCIOs (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
Maximum ramp time for all VCCs should be 0V to nominal
voltage in 100 ms.
Configuration Parameters
Parameter
Description
Min.
Unit
tRECONFIG
Reconfig pin LOW time before it goes HIGH
200
ns
相關PDF資料
PDF描述
CY39030Z144-83BBC LOADABLE PLD, 15 ns, PBGA144
CY39030Z144-83BBI LOADABLE PLD, 15 ns, PBGA144
CY39030Z208-222NC LOADABLE PLD, 7 ns, PQFP208
CY39030Z256-222BBC LOADABLE PLD, 7 ns, PBGA256
CY39030Z256-222MBC LOADABLE PLD, 7 ns, PBGA256
相關代理商/技術參數(shù)
參數(shù)描述
CY39030Z208-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39030Z208-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39030Z208-125BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39030Z208-125BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39030Z208-125MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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