參數(shù)資料
型號： CY39050V208-222NTC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 7 ns, PQFP208
封裝： THERMALLY ENHANCED, QFP-208
文件頁數(shù)： 15/57頁
文件大小： 1166K
代理商： CY39050V208-222NTC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 22 of 57
Channel Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Dual Port Asynchronous Mode Parameters
tCHMAA
Channel memory access time. Delay from address change to read data out
tCHMPWE
Write enable pulse width
tCHMSA
Address set-up to the beginning of write enable with both signals from the same I/O block
tCHMHA
Address hold after the end of write enable with both signals from the same I/O block
tCHMSD
Data set-up to the end of write enable
tCHMHD
Data hold after the end of write enable
tCHMBA
Channel memory asynchronous dual port address match (busy access time)
Dual Port Synchronous Mode Parameters
tCHMCYC1
Clock cycle time for flow through read and write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
tCHMCYC2
Clock cycle time for pipelined read and write operations (from channel memory input register through the
memory to channel memory output register)
tCHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
tCHMH
Address, data, and WE hold time of pin inputs, relative to a global clock
tCHMDV1
Global clock to data valid on output pins for flow through data
tCHMDV2
Global clock to data valid on output pins for pipelined data.
tCHMBDV
Channel memory synchronous dual-port address match (busy, clock to data valid)
tCHMMACS1
Channel memory input clock to macrocell clock in the same cluster
tCHMMACS2
Channel memory output clock to macrocell clock in the same cluster
tMACCHMS1
Macrocell clock to channel memory input clock in the same cluster
tMACCHMS2
Macrocell clock to channel memory output clock in the same cluster
Synchronous FIFO Data Parameters
tCHMCLK
Read and write minimum clock cycle time
tCHMFS
Data, read enable, and write enable set-up time relative to pin inputs
tCHMFH
Data, read enable, and write enable hold time relative to pin inputs
tCHMFRDV
Data access time to output pins from rising edge of read clock (read clock to data valid)
tCHMMACS
Channel memory FIFO read clock to macrocell clock for read data
tMACCHMS
Macrocell clock to channel memory FIFO write clock for write data
Synchronous FIFO Flag Parameters
tCHMFO
Read or write clock to respective flag output at output pins
tCHMMACF
Read or write clock to macrocell clock with FIFO flag
tCHMFRS
Master Reset Pulse Width
tCHMFRSR
Master Reset Recovery Time
tCHMFRSF
Master Reset to Flag and Data Output Time
tCHMSKEW1
Read/Write Clock Skew Time for Full Flag
tCHMSKEW2
Read/Write Clock Skew Time for Empty Flag
tCHMSKEW3
Read/Write Clock Skew Time for Boundary Flags
Internal Parameters
tCHMCHAA
Asynchronous channel memory access time from input of channel memory to output of channel memory
相關(guān)PDF資料
PDF描述
CY39050V256-222BBC LOADABLE PLD, 7 ns, PBGA256
CY39050V388-222MGC LOADABLE PLD, 7 ns, PBGA388
CY39050V484-222MBC LOADABLE PLD, 7 ns, PBGA484
CY39050Z208-222NC LOADABLE PLD, 7 ns, PQFP208
CY39050Z256-222BBC LOADABLE PLD, 7 ns, PBGA256
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