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參數(shù)資料
| 型號： | CY62127BVLL-70BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64K x 16 Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 384K |
| 代理商： | CY62127BVLL-70BAI |
CY62127DV30
MoBL
Document #: 38-05229 Rev. *D
Page 6 of 12
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[16,17]
Read Cycle No. 2 (OE Controlled)
[16,17, 18]
Notes:
16.Device is continuously selected. OE, CE = V
IL
, BHE, BLE = V
IL
.
17.WE is HIGH for Read cycle.
18.Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62127BVLL-70ZI | 64K x 16 Static RAM |
| CY62127DV30LL-45ZSXI | Circular Connector; Body Material:Aluminum; Series:PT00; Number of Contacts:25; Connector Shell Size:22; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Socket |
| CY62127DV30L-55ZSXI | Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:41; Connector Shell Size:22; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Pin; Insert Arrangement:22-41 |
| CY62127DV30L-70ZSI | 1 Mb (64K x 16) Static RAM |
| CY62127DV30LL-70ZSI | 2 X 4 PR #24 DUAL DATATWIST |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62127BVLL-70BKI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62127BVLL-70ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:64K x 16 Static RAM |
| CY62127BVLL-70ZIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 1M-Bit 64K x 16 70ns 44-Pin TSOP-II T/R |
| CY62127DV18 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1M (64K x 16) Static RAM |
| CY62127DV18_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 Mb (64K x 16) Static RAM |
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