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參數(shù)資料
| 型號： | CY62127DV18L-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1M (64K x 16) Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 384K |
| 代理商： | CY62127DV18L-55BVI |
CY62127DV30
MoBL
Document #: 38-05229 Rev. *D
Page 4 of 12
Capacitance
[7]
AC Test Loads and Waveforms
[8]
Data Retention Waveform
[10]
Notes:
7. Tested initially and after any design or proces changes that may affect these parameters.
8. Test condition for the 45-ns part is a load capacitance of 30 pF.
9. Full device operation requires linear V
ramp from V
to V
> 200
μ
s.
10.BHE
BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both.
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance
Parameter
θ
JA
θ
JC
Description
Test Conditions
FBGA TSOP II Unit
55
76
12
11
Thermal Resistance (Junction to Ambient)
[7]
Thermal Resistance (Junction to Case)
[7]
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
°C/W
°C/W
Data Retention Characteristics
Parameter
V
DR
I
CCDR
Description
Conditions
Min.
1.5
Typ
.
[4]
Max.
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
V
CC
=1.5V, CE > V
CC
0.2V,
V
IN
> V
CC
0.2V or V
IN
< 0.2V
L
LL
4
3
t
CDR[7]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
t
R[9]
200
μ
s
V
CC
Typ
V
CC
OUTPUT
R2
C = 50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
TH
éVENIN EQUIVALENT
R
TH
ALL INPUT PULSES
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
Parameters
R1
R2
R
TH
V
TH
3.0V (2.7
–
3.6V)
1103
1554
645
1.75
Unit
V
2.5V (2.2
–
2.7V)
16600
15400
8000
1.2
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
t
R
CEor
V
CC
BHE.BLE
VCC(min.)
VCC(min.)
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