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參數(shù)資料
| 型號(hào)： | CY62127DV18LL-55BVI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1M (64K x 16) Static RAM |
| 中文描述： | 64K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, VFBGA-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 384K |
| 代理商： | CY62127DV18LL-55BVI |
CY62127DV30
MoBL
Document #: 38-05229 Rev. *D
Page 5 of 12
Switching Characteristics
(Over the Operating Range)
[11]
Parameter
Description
CY62127DV30-45
[8]
CY62127DV30-55
CY62127DV30-70
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[13]
t
HZBE
Write Cycle
[15]
Read Cycle Time
45
55
70
ns
Address to Data Valid
45
55
70
ns
Data Hold from Address Change
10
10
10
ns
CE LOW to Data Valid
45
55
70
ns
OE LOW to Data Valid
OE LOW to Low Z
[12]
OE HIGH to High Z
[12,14]
CE LOW to Low Z
[12]
CE HIGH to High Z
[12,14]
25
25
35
ns
5
5
5
ns
15
20
25
ns
10
10
10
ns
20
20
25
ns
CE LOW to Power-up
0
0
0
ns
CE HIGH to Power-down
45
55
70
ns
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[12]
BLE/BHE HIGH to High-Z
[12,14]
45
55
70
ns
5
5
5
ns
15
20
25
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
45
55
70
ns
CE LOW to Write End
40
40
60
ns
Address Set-up to Write End
40
40
60
ns
Address Hold from Write End
0
0
0
ns
Address Set-up to Write Start
0
0
0
ns
WE Pulse Width
35
40
50
ns
BLE/BHE LOW to Write End
40
40
60
ns
Data Set-up to Write End
25
25
30
ns
Data Hold from Write End
WE LOW to High Z
[12,14]
WE HIGH to Low Z
[12]
0
0
0
ns
15
20
25
ns
10
10
5
ns
Notes:
11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
.
12.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
13.If both byte enables are toggled together, this value is 10 ns.
14.t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
15.The internal Write time of the memory is defined by the overlap of WE, CE = V
, BHE and/or BLE = V
.
All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY62127DV18LL-55ZI | 1M (64K x 16) Static RAM |
| CY62127DV30 | 1 Mb (64K x 16) Static RAM |
| CY62127DV30L | 1 Mb (64K x 16) Static RAM |
| CY62127DV30L-55BVI | 1 Mb (64K x 16) Static RAM |
| CY62127BV | 64K x 16 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62127DV18LL-55ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 Mb (64K x 16) Static RAM |
| CY62127DV20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Memory |
| CY62127DV20L-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1M (64K x 16) Static RAM |
| CY62127DV20L-55ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1M (64K x 16) Static RAM |
| CY62127DV20LL-55BVI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1M (64K x 16) Static RAM |
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