參數(shù)資料
型號(hào): CY62127DV30LL-70BVI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 1 Mb (64K x 16) Static RAM
中文描述: 64K X 16 STANDARD SRAM, 70 ns, PBGA48
封裝: 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 384K
代理商: CY62127DV30LL-70BVI
CY62127DV30
MoBL
Document #: 38-05229 Rev. *D
Page 6 of 12
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[16,17]
Read Cycle No. 2 (OE Controlled)
[16,17, 18]
Notes:
16.Device is continuously selected. OE, CE = V
IL
, BHE, BLE = V
IL
.
17.WE is HIGH for Read cycle.
18.Address valid prior to or coincident with CE, BHE, BLE transition LOW.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
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