參數(shù)資料
型號(hào): CY62137CVSL
廠商: Cypress Semiconductor Corp.
英文描述: 2-Mbit (128K x 16) Static RAM
中文描述: 2兆位(128K的× 16)靜態(tài)RAM
文件頁(yè)數(shù): 5/13頁(yè)
文件大?。?/td> 339K
代理商: CY62137CVSL
CY62137CV30/33 MoBL
CY62137CV MoBL
Document #: 38-05201 Rev. *G
Page 5 of 13
AC Test Loads and Waveforms
Parameters
3.0V
3.3V
Unit
R1
1105
1216
R2
1550
1374
R
TH
645
645
V
TH
1.75
1.75
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.
[4]
Max.
Unit
V
DR
V
CC
for Data Retention
1.5
V
cc(max)
V
I
CCDR
Data Retention Current
V
CC
= 1.5V
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
LL
Ind’l
1
6
μ
A
Auto
8
SL
Ind’l
4
t
CDR[6]
t
R[7]
Chip Deselect to Data Retention Time
0
ns
Operation Recovery Time
t
RC
ns
Data Retention Waveform
[8]
Notes:
7. Full-device AC operation requires linear V
ramp from V
to V
> 100
μ
s or stable at V
> 100
μ
s.
8. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise TIme: 1 V/ns
Fall Time: 1 V/ns
V
CC(min.)
V
CC(min.)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
CE or
V
CC
BHE.BLE
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