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| 型號(hào)： | CY62147EV18LL-55BVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 55 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 388K |
| 代理商： | CY62147EV18LL-55BVXI |
CY62147EV18 MoBL2
Document #: 38-05441 Rev. *F
Page 5 of 12
Switching Characteristics
Over the Operating Range
[11, 12]
Parameter
Description
55 ns
Unit
Min
Max
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[15]
Read Cycle Time
55
ns
Address to Data Valid
55
ns
Data Hold from Address Change
10
ns
CE LOW to Data Valid
55
ns
OE LOW to Data Valid
OE LOW to Low Z
[13]
OE HIGH to High Z
[13, 14]
CE LOW to Low Z
[13]
CE HIGH to High Z
[13, 14]
25
ns
5
ns
18
ns
10
ns
18
ns
CE LOW to Power Up
0
ns
CE HIGH to Power Down
55
ns
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[13]
BLE/BHE HIGH to High Z
[13, 14]
55
ns
10
ns
18
ns
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
45
ns
CE LOW to Write End
35
ns
Address Setup to Write End
35
ns
Address Hold from Write End
0
ns
Address Setup to Write Start
0
ns
WE Pulse Width
35
ns
BLE/BHE LOW to Write End
Data Setup to Write End
35
ns
25
ns
Data Hold from Write End
0
ns
WE LOW to High Z
[13, 14]
WE HIGH to Low Z
[13]
18
ns
10
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels
of 0 to V
, and output loading of the specified I
/I
as shown in the
“AC Test Loads and Waveforms”
on page 4 section.
12.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
application note AN13842
for further clarification.
13.At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
14.t
, t
, t
, and t
transitions are measured when the output enters a high impedence state
15.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE, BLE or both = V
. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62147EV18LL-55BVXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M MoBL Ultra Lo PWR HI SPD MicroPWR RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62147EV30 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62147EV30_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM |
| CY62147EV30_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256K x 16) Static RAM Wide voltage range: 2.20 V to 3.60 V |
| CY62147EV30_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4-Mbit (256Kx16) Satic RAM |
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