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參數(shù)資料
| 型號(hào)： | CY62147EV30LL-55ZSXE |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (256K x 16) Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 55 ns, PDSO44 |
| 封裝： | LEAD FREE, TSOP2-44 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 517K |
| 代理商： | CY62147EV30LL-55ZSXE |
CY62147EV30 MoBL
Document #: 38-05440 Rev. *E
Page 12 of 12
Document History Page
Document Title: CY62147EV30 MoBL
4-Mbit (256K x 16) Static RAM
Document Number: 38-05440
REV.
ECN NO.
Issue Date
Orig. of
Change
AJU
SYT
Description of Change
**
*A
201861
247009
01/13/04
See ECN
New Data Sheet
Changed from Advanced Information to Preliminary
Moved Product Portfolio to Page 2
Changed Vcc stabilization time in footnote #8 from 100
μ
s to 200
μ
s
Removed Footnote #15(t
LZBE
) from Previous Revision
Changed I
CCDR
from 2.0
A to 2.5
μ
A
Changed typo in Data Retention Characteristics(t
R
) from 100
μ
s to t
RC
ns
Changed t
OHA
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed t
HZOE
, t
HZBE
, t
HZWE
from 12 to 15 ns for 35 ns Speed Bin and 15 to
18 ns for 45 ns Speed Bin
Changed t
SCE
and t
BW
from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns
for 45 ns Speed Bin
Changed t
HZCE
from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45
ns Speed Bin
Changed t
SD
from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed t
DOE
from 15 to 18 ns for 35 ns Speed Bin
Changed Ordering Information to include Pb-Free Packages
Changed from Preliminary information to Final
Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62147EV30
Changed ball E3 from DNU to NC.
Removed redundant foot note on DNU.
Changed I
CC
(Max) value from 2 mA to 2.5 mA and I
CC
(Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed I
CC
(Typ) value from 12 mA to 15 mA at f = f
max
Changed I
SB1
and I
SB2
Typ values from 0.7
μ
A to 1
μ
A and Max values from
2.5
μ
A to 7
μ
A.
Changed I
CCDR
from 2.5
μ
A to 7
μ
A.
Added I
CCDR
typical value.
Changed AC test load capacitance from 50 pF to 30 pF on Page #4.
Changed t
LZOE
from 3 ns to 5 ns
Changed t
LZCE
, t
LZBE
and t
LZWE
from 6 ns to 10 ns
Changed t
HZCE
from 22 ns to 18 ns
Changed t
PWE
from 30 ns to 35 ns.
Changed t
SD
from 22 ns to 25 ns.
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering information table and replaced the Package Name
column with Package Diagram.
Included Automotive Range in product offering
Updated the Ordering Information
Added Preliminary Automotive-A information
Added footnote #9 related to I
SB2
and
I
CCDR
Added footnote #14 related AC timing parameters
Converted Automotive-A and Automotive -E specs from preliminary to final
*B
414807
See ECN
ZSD
*C
464503
See ECN
NXR
*D
925501
See ECN
VKN
*E
1045701
See ECN
VKN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62147EV30LL-55ZSXET | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M MoBL Ultra Lo PWR HI SPD MicroPWR RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62147LL-70BAI | 制造商:Cypress Semiconductor 功能描述: |
| CY62147V | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4M (256K x 16) Static RAM |
| CY62147V18-85BAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| CY62147V18LL-70BAI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
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