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參數(shù)資料
| 型號： | CY7C016AV-20JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM |
| 中文描述： | 16K X 9 DUAL-PORT SRAM, 20 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 301K |
| 代理商： | CY7C016AV-20JC |
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 11 of 20
Notes:
37. CE = HIGH for the duration of the above timing (both write and read cycle).
38. I/O
= I/O
= LOW (request semaphore); CE
= CE
= HIGH.
39. Semaphores are reset (available to both ports) at cycle start.
40. If t
SPS
is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Switching Waveforms
(continued)
t
SOP
t
SAA
VALID ADRESS
VALID ADRESS
t
HD
DATA
IN
VALID
DATA
OUT
VALID
t
OHA
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE
READ CYCLE
OE
R/W
I/O
0
SEM
A
0
–
A
2
Semaphore Read After Write Timing, Either Side
[37]
MATCH
t
SPS
A
0L
–
A
2L
MATCH
R/W
L
SEM
L
A
0R
–
A
2R
R/W
R
SEM
R
Timing Diagram of Semaphore Contention
[38, 39, 40]
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| CY7C016AV-25JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM |
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| CY7C017A-15JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:32K/16K x8, 32K/16K x9 Dual-Port Static RAM |
| CY7C017A-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
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