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參數(shù)資料
| 型號： | CY7C025-55JC |
| 英文描述： | SRAM|8KX16|CMOS|LDCC|84PIN|PLASTIC |
| 中文描述： | 靜態(tài)存儲器| 8KX16 |的CMOS | LDCC | 84PIN |塑料 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 301K |
| 代理商： | CY7C025-55JC |
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 10 of 20
Notes:
29. R/W must be HIGH during all address transitions.
30. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
31. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
32. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified tPWE.
33. Transition is measured
±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. To access RAM, CE = VIL, SEM = VIH.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE
tLZWE
Write Cycle No. 1: R/W Controlled Timing[29, 30, 31, 32]
[33]
[32]
[34]
[35]
tAW
tWC
tSCE
tHD
tSD
tHA
CE
R/W
DATA IN
ADDRESS
tSA
Write Cycle No. 2: CE Controlled Timing[29, 30, 31, 36]
[34]
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| CY7C025-55JI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY |
| CY7C025-55JXC | 功能描述:IC SRAM 128KBIT 55NS 84PLCC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C025-55JXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY |
| CY7C025AV | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM |
| CY7C025AV WAF | 制造商:Cypress Semiconductor 功能描述: |
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