參數(shù)資料
型號(hào): CY7C0852AV-133BBC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 128K X 36 DUAL-PORT SRAM, 4 ns, PBGA172
封裝: 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, FBGA-172
文件頁數(shù): 18/32頁
文件大小: 971K
代理商: CY7C0852AV-133BBC
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Document #: 38-06070 Rev. *H
Page 25 of 32
Figure 21. Left_Port (L_Port) Write to Right_Port (R_Port) Read[39, 40, 41]
Switching Waveforms (continued)
tSA
tHA
tSW
tHW
tCH2
tCL2
tCYC2
CLKL
R/WL
An
Dn
tCKHZ
tHD
tSA
An
tHA
Qn
tDC
tCCS
tSD
tCKLZ
tCH2
tCL2
tCYC2
tCD2
L_PORT
ADDRESS
L_PORT
DATAIN
CLKR
R/WR
R_PORT
ADDRESS
R_PORT
DATAOUT
Notes
39. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
40. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data is Read out.
41. If tCCS < minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS
> minimum specified value, then R_Port is Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
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