參數(shù)資料
型號(hào): CY7C09099V-12AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 8 DUAL-PORT SRAM, 25 ns, PQFP100
封裝: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件頁數(shù): 16/28頁
文件大?。?/td> 657K
代理商: CY7C09099V-12AXC
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 23 of 28
Read/Write and Enable Operation [58, 59, 60]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
I/O0–I/O9
Operation
X
H
X
High Z
Deselected[61]
X
L
X
High Z
Deselected[61]
X
L
H
L
DIN
Write
L
H
DOUT
Read[61]
H
X
L
H
X
High Z
Outputs Disabled
Address Counter Control Operation [58, 62, 63, 64]
Address
Previous
Address
CLK
ADS
CNTEN
CNTRST
I/O
Mode
Operation
X
L
Dout(0)
Reset
Counter Reset to Address 0
An
X
L
X
H
Dout(n)
Load
Address Load into Counter
X
An
H
Dout(n)
Hold
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1)
Increment Counter Enabled—Internal Address
Generation
Notes
58. “X” = “Don’t Care”, “H” = VIH, “L” = VIL.
59. ADS, CNTEN, CNTRST = “Don’t Care.”
60. OE is an asynchronous input signal.
61. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
62. CE0 and OE = VIL; CE1 and R/W = VIH.
63. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
64. Counter operation is independent of CE0 and CE1.
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