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參數(shù)資料
| 型號： | CY7C09099V-7AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM |
| 中文描述： | 128K X 8 DUAL-PORT SRAM, 18 ns, PQFP100 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 657K |
| 代理商： | CY7C09099V-7AXI |
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CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 3 of 28
Functional Description
The CY7C09089V/99V and CY7C09179V/99V are high speed
synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port
static RAMs. Two ports are provided, permitting independent,
simultaneous access for reads and writes to any location in
memory.[4] Registers on control, address, and data lines enable
minimal setup and hold times. In pipelined output mode, data is
registered for decreased cycle time. Clock to data valid
to bypass the pipelined output register to eliminate access
latency. In flow-through mode, data is available tCD1 = 18 ns after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the
LOW-to-HIGH transition of the clock signal. The internal write
pulse is self-timed to enable the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. The
use of multiple Chip Enables enables easier banking of multiple
chips for depth expansion configurations. In the pipelined mode,
one cycle is required with CE0 LOW and CE1 HIGH to reactivate
the outputs.
Counter enable inputs are provided to stall the operation of the
address input and use the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted, the
address counter increments on each LOW-to-HIGH transition of
that port’s clock signal. This reads/writes one word from/into
each successive address location until CNTEN is deasserted.
The counter can address the entire memory array and loops
back to the start. Counter Reset (CNTRST) is used to reset the
burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Notes
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C09179V-12AXC | 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM |
| CY7C09179V-6AXC | 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM |
| CY7C09199V-9AXC | 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM |
| CY7C09159AV-12AXC | 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM |
| CY7C1009B-20VXC | 128K X 8 STANDARD SRAM, 20 ns, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C09099V-9AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 1M-Bit 128K x 8 20ns/9ns 100-Pin TQFP |
| CY7C09099V-9AI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 1M-Bit 128K x 8 20ns/9ns 100-Pin TQFP |
| CY7C09159AV-12AC | 功能描述:IC SRAM 72KBIT 12NS 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| CY7C09159AV-12AXC | 功能描述:靜態(tài)隨機存取存儲器 3.3V 8Kx9 COM Sync Dual Port 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C09159AV-9AC | 制造商:Cypress Semiconductor 功能描述: |
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