參數(shù)資料
型號(hào)： CY7C09099V
英文描述： Memory
中文描述： 內(nèi)存
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 301K
代理商： CY7C09099V
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 2 of 20
Functional Description
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and
32K x8/9 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are pro-
vided, permitting independent, asynchronous access for reads
and writes to any location in memory. The devices can be uti-
lized as standalone 8/9-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 16/18-bit or
wider master/slave dual-port static RAM. An M/S pin is provid-
ed for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include interpro-
cessor/multiprocessor designs, communications status buffer-
ing, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Select (CE) pin.
Pin Configurations
Notes:
4.
I/O8L on the CY7C139AV.
5.
I/O8R on the CY7C139AV.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
Top View
68-Pin PLCC
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 33 34 35 36 37 38 39 40 41 42 43
5 4 3 2 1 68
66 65 64 63 62 61
A
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
A
2728 29 30
98 7 6
47
46
45
44
A1R
A2R
A3R
A4R
I/O3R
I/O4R
I/O5R
I/O6R
25
26
6L
7L
A
8L
A
9L
A
10L
11L
V
CC
NC
CE
L
SEM
L
R/W
L
OE
L
NC
I/O
1L
0L
A
6R
7R
A
8R
A
9R
A
10
R
NC
CE
R
SE
M
R
R/W
R
OE
R
I/O
7R
GND
A
11
R
A
5R
A5L
NC
CY7C138AV (4K x 8)
[5
]
[4
]
NC
CY7C139AV (4K x 9)
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