參數(shù)資料
型號: CY7C09179A-7AC
英文描述: SYNC SRAM|32KX9|CMOS|QFP|100PIN|PLASTIC
中文描述: 同步靜態(tài)存儲器| 32KX9 |的CMOS | QFP封裝| 100引腳|塑料
文件頁數(shù): 19/20頁
文件大?。?/td> 301K
代理商: CY7C09179A-7AC
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 8 of 20
Data Retention Mode
The CY7C0138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data reten-
tion:
1. Chip enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 volts).
Notes:
22. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
23. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
tWB
R/W HIGH after BUSY (Slave)
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
15
17
ns
tBDD
[22]
BUSY HIGH to Data Valid
20
25
ns
INTERRUPT TIMING[21]
tINS
INT Set Time
20
ns
tINR
INT Reset Time
20
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)
10
12
ns
tSWRD
SEM Flag Write to Read Time
5
ns
tSPS
SEM Flag Contention Window
5
ns
tSAA
SEM Address Access Time
20
25
ns
Switching Characteristics Over the Operating Range[15] (continued)
Parameter
Description
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Unit
-20
-25
Min.
Max.
Min.
Max.
Timing
Parameter
Test Conditions[23]
Max.
Unit
ICCDR1
@ VCCDR = 2V
50
A
Data Retention Mode
3.0V
VCC > 2.0V
VCC to VCC – 0.2V
VCC
CE
tRC
V
IH
相關(guān)PDF資料
PDF描述
CY7C09179A-9AC SYNC SRAM|32KX9|CMOS|QFP|100PIN|PLASTIC
CY7C09179V Memory
CY7C09179V-9AC x9 Dual-Port SRAM
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