參數(shù)資料
型號(hào): CY7C09199V-9AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 9 DUAL-PORT SRAM, 20 ns, PQFP100
封裝: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件頁數(shù): 5/28頁
文件大?。?/td> 657K
代理商: CY7C09199V-9AXC
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 13 of 28
Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = VIH)[23, 24, 25, 26]
Switching Waveforms (continued)
tCH2
tCL2
tCYC2
tSC
tHC
tSW
tHW
tSA
tHA
An
An+1
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
An+2
An+3
tSC
tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
Qn
Qn+1
Qn+2
1 Latency
Notes
23. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
24. ADS = VIL, CNTEN and CNTRST = VIH.
25. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock.
26. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
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