參數(shù)資料
型號: CY7C1061AV33-10ZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 16-Mbit (1M x 16) Static RAM
中文描述: 1M X 16 STANDARD SRAM, 10 ns, PDSO54
封裝: 22.40 X 11.84 MM, 1 MM HEIGHT, LEAD FREE, TSOP2-54
文件頁數(shù): 3/10頁
文件大?。?/td> 566K
代理商: CY7C1061AV33-10ZXC
CY7C1061AV33
Document #: 38-05256 Rev. *G
Page 3 of 10
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage on V
CC
to Relative GND
[3]
...–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[3]
...................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
...............................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
Commercial
Industrial
3.3V
±
0.3V
DC Electrical Characteristics
(Over the Operating Range)
Parameter
Description
Test Conditions
–10
–12
Unit
Min
2.4
Max
Min
2.4
Max
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Leakage Current
Output Leakage Current GND < V
O
< V
CC
, Output Disabled
V
CC
Operating
Supply Current
f = f
max
= 1/t
RC
I
OH
= –4.0 mA
I
OL
= 8.0 mA
V
V
V
V
μ
A
μ
A
mA
mA
mA
0.4
0.4
2.0
–0.3
–1
–1
V
CC
+ 0.3
0.8
+1
+1
275
275
70
2.0
–0.3
–1
–1
V
CC
+ 0.3
0.8
+1
+1
260
260
70
GND < V
I
< V
CC
V
CC
= max,
Commercial
Industrial
I
SB1
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
CE
2
<= V
IL,
max V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
max
CE
2
<= 0.3V
max V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
I
SB2
Commercial/
Industrial
50
50
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
IO Capacitance
Test Conditions
TSOP II
6
8
FBGA
8
10
Unit
pF
pF
T
A
= 25
°
C, f = 1 MHz, V
CC
= 3.3V
AC Test Loads and Waveforms
[5]
Notes
3. V
(min) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
(3.0V). As soon as 1 ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE
(a)
(b)
R1 317
R2
351
Rise time > 1V/ns
Fall time:
> 1V/ns
(c)
OUTPUT
50
Z
0
= 50
V
TH
= 1.5V
30 pF* * Capacitive Load consists of all com-
ponents of the test environment.
[+] Feedback
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