參數(shù)資料
型號(hào)： CY7C1061AV33-8ZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： JT 37C 37#22D SKT PLUG
中文描述： 1M X 16 STANDARD SRAM, 8 ns, PDSO54
封裝： TSOP2-54
文件頁(yè)數(shù)： 1/11頁(yè)
文件大?。?/td> 269K
代理商： CY7C1061AV33-8ZI
PRELIMINARY
1M x 16 Static RAM
CY7C1061AV25
Cypress Semiconductor Corporation
Document #: 38-05331 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 27, 2003
Features
High speed
—t
AA
= 8, 10, 12 ns
Low active power
—1080 mW (max.)
Operating voltages of 2.5 ± 0.2V
1.5V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
and CE
2
features
Functional Description
The CY7C1061AV25 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip
(CE
1
LOW and CE
2
HIGH) while forcing the Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
), is written into the location
specified on the address pins (A
0
through A
19
). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
19
).
Reading from the device is accomplished by enabling the chip
by taking CE
1
LOW and CE
2
HIGH while forcing the Output
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table at the back of this data
sheet for a complete description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH / CE
2
LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or during a
Write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1061AV25 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball fine-pitch ball grid array (FBGA) package.
Selection Guide
-8
8
300
300
50
-10
10
275
275
50
-12
12
260
260
50
Unit
ns
mA
Maximum Access Time
Maximum Operating Current
Commercial
Industrial
Commercial/Industrial
Maximum CMOS Standby Current
mA
Logic Block Diagram
Pin Configuration
TSOP II (Top View)
WE
CE
2
A
19
A
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
41
43
42
16
17
29
28
A
5
A
6
A
7
A
8
A
9
NC
A
0
A
1
OE
V
SS
V
SS
I/O
15
A
17
A
16
A
15
A
2
1
V
CC
I/O
2
V
SS
I/O
0
V
CC
I/O
1
CE
A
3
A
4
18
19
20
21
I/O
3
27
25
26
22
23
24
I/O
6
I/O
5
V
CC
I/O
4
I/O
7
V
BLE
A
10
V
CC
I/O
13
I/O
14
I/O
12
I/O
10
I/O
9
V
CC
I/O
8
A
14
A
13
A
12
A
11
44
46
45
47
50
49
48
51
53
52
54
DNU (Do Not Use)
I/O
11
V
SS
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
1M x 16
ARRAY
4096 x 4096
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
I/O
0
–
I/O
7
BLE
I/O
8
–
I/O
15
OE
1
WE
2
BHE
A
1
相關(guān)PDF資料
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