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參數(shù)資料
| 型號： | CY7C1061DV33-10ZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16-Mbit (1M x 16) Static RAM |
| 中文描述： | 1M X 16 STANDARD SRAM, 10 ns, PDSO54 |
| 封裝： | LEAD FREE, TSOP2-54 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 401K |
| 代理商： | CY7C1061DV33-10ZXI |
PRELIMINARY
16-Mbit (1M x 16) Static RAM
CY7C1061DV33
Cypress Semiconductor Corporation
Document #: 38-05476 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 14, 2006
Features
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 125 mA @ 10 ns
Low CMOS standby power
— I
SB2
= 25 mA
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
and CE
2
features
Available in Pb-free 54-pin TSOP II package and 48-ball
VFBGA packages
Functional Description
The CY7C1061DV33 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip
(CE
1
LOW and CE
2
HIGH) while forcing the Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
), is written into the location
specified on the address pins (A
0
through A
19
). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
19
).
Reading from the device is accomplished by enabling the chip
by taking CE
1
LOW and CE
2
HIGH while forcing the Output
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table at the back of this data
sheet for a complete description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH/CE
2
LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or during a
Write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1061DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball Very fine-pitch ball grid array (VFBGA) package
54-pin TSOP II (Top View)
WE
CE
2
A
19
A
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
41
43
42
16
17
29
28
A
5
A
6
A
7
A
8
A
9
NC
A
0
A
1
OE
V
SS
V
SS
I/O
15
A
17
A
16
A
15
A
2
1
V
CC
I/O
2
V
SS
I/O
0
V
CC
I/O
1
CE
A
3
A
4
18
19
20
21
I/O
3
27
25
26
22
23
24
I/O
6
I/O
5
V
I/O
4
I/O
7
V
BLE
A
10
V
CC
I/O
13
I/O
14
I/O
12
I/O
10
I/O
9
V
CC
I/O
8
A
14
A
13
A
12
A
11
44
46
45
47
50
49
48
51
53
52
54
NC
I/O
11
V
SS
Logic Block Diagram
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
1M x 16
ARRAY
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
I/O
0
–I/O
7
OE
BLE
I/O
8
–I/O
15
CE
1
WE
BHE
A
1
CE
2
Pin Configuration
[+] Feedback
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| CY7C1061G30-10ZSXI | 功能描述:IC SRAM 16MBIT 10NS 54TSOP 制造商:cypress semiconductor corp 系列:- 包裝:托盤 零件狀態(tài):在售 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:16M（1M x 16） 速度:10ns 接口:并聯(lián) 電壓 - 電源:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:54-TSOP（0.400"，10.16mm 寬） 供應(yīng)商器件封裝:54-TSOP II 標(biāo)準(zhǔn)包裝:108 |
| CY7C1061G30-10ZSXIT | 功能描述:IC SRAM 16MBIT 10NS 54TSOP 制造商:cypress semiconductor corp 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 存儲器類型:易失 存儲器格式:SRAM 技術(shù):SRAM - 異步 存儲容量:16Mb （1M x 16） 寫周期時(shí)間 - 字，頁:10ns 訪問時(shí)間:10ns 存儲器接口:并聯(lián) 電壓 - 電源:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:54-TSOP（0.400"，10.16mm 寬） 供應(yīng)商器件封裝:54-TSOP II 標(biāo)準(zhǔn)包裝:1 |
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| CY7C1062 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1062AV25-10BGC | 制造商:Cypress Semiconductor 功能描述: |
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