參數(shù)資料
型號(hào): CY7C1069AV33
廠商: Cypress Semiconductor Corp.
英文描述: 2M x 8 Static RAM
中文描述: 200萬(wàn)× 8靜態(tài)RAM
文件頁(yè)數(shù): 3/9頁(yè)
文件大小: 249K
代理商: CY7C1069AV33
CY7C1069AV33
Document #: 38-05255 Rev. *D
Page 3 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°C to +150°C
Ambient Temperature with
Power Applied............................................. –55
°C to +125°C
Supply Voltage on VCC to Relative GND
[1] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0
°C to +70°C
3.3V
± 0.3V
Industrial
–40
°C to +85°C
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
–8
–10
–12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
VOH
Output HIGH Voltage
VCC = Min.,
IOH = –4.0 mA
2.4
V
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
V
VIH
Input HIGH Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
V
VIL
Input LOW Voltage[1]
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
IIX
Input Load Current
GND < VI < VCC
–1+1
A
IOZ
Output Leakage Current GND < VOUT < VCC, Output
Disabled
–1+1
A
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX
= 1/tRC
Commercial
300
275
260
mA
Industrial
300
275
260
mA
ISB1
Automatic CE
Power-down Current
—TTL Inputs
CE2 < VIL,
Max. VCC, SCE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
70
mA
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
CE2 < 0.3V
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Commercial/
Industrial
50
mA
Capacitance[2]
Parameter
Package
Description
Test Conditions
Max.
Unit
CIN
Z54
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
pF
BA48
8pF
COUT
Z54
I/O Capacitance
8
pF
BA48
10
pF
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2.
Tested initially and after any design or process changes that may affect these parameters.
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