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參數(shù)資料
| 型號： | CY7C106B |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 4 Static RAM |
| 中文描述： | 256K × 4靜態(tài)RAM |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 161K |
| 代理商： | CY7C106B |
CY7C106B
CY7C1006B
Document #: 38-05037 Rev. **
Page 5 of 10
Switching Characteristics Over the Operating Range[5]
7C106B-12
7C1006B-12
7C106B-15
7C1006B-15
7C106B-20
7C1006B-20
7C106B-25
7C1006B-25
7C106B-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
Read Cycle Time
12
15
20
25
35
ns
tAA
Address to Data Valid
12
15
20
25
35
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE LOW to Data Valid
12
15
20
25
35
ns
tDOE
OE LOW to Data Valid
6
7
8
10
ns
tLZOE
OE LOW to Low Z
0
ns
tHZOE
OE HIGH to High Z[6, 7]
67
8
10
ns
tLZCE
CE LOW to Low Z[7]
333
3
ns
tHZCE
CE HIGH to High Z[6, 7]
67
8
10
ns
tPU
CE LOW to Power-Up
0
ns
tPD
CE HIGH to Power-Down
12
15
20
25
35
ns
WRITE CYCLE[8, 9]
tWC
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
tAW
Address Set-Up to Write End
10
12
15
20
25
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[7]
233
3
ns
tHZWE
WE LOW to High Z[6, 7]
67
8
10
ns
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30–pF load capacitance.
6.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8.
The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9.
The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C106B-20VC | 制造商:Rochester Electronics LLC 功能描述:1MB (256K X 4)- FAST ASYNCH SRAM - Bulk |
| CY7C106B-20VCT | 制造商:Rochester Electronics LLC 功能描述:1MB (256K X 4)- FAST ASYNCH SRAM - Bulk |
| CY7C106B-25VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 1M-Bit 256K x 4-Bit 25ns 28-Pin SOJ 制造商:Rochester Electronics LLC 功能描述:1MB (256K X 4)- FAST ASYNCH SRAM - Bulk |
| CY7C106B-25VCT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C106BN-15VC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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