CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Document Number: 001-06621 Rev. *D
Page 2 of 27
Logic Block Diagram (CY7C1146V18)
Logic Block Diagram (CY7C1157V18)
CLK
A(19:0)
Gen.
K
Control
Logic
Address
Register
Read
Add.
D
e
code
Read Data Reg.
R/W
DQ[7:0]
Output
Logic
Reg.
8
16
8
NWS[1:0]
VREF
W
rite
Add.
D
e
code
8
LD
Control
20
1M
x
8
Array
1M
x
8
Arr
a
y
Write
Reg
Write
Reg
CQ
R/W
DOFF
QVLD
8
CLK
A(19:0)
Gen.
K
Control
Logic
Address
Register
Read
Add.
De
code
Read Data Reg.
R/W
DQ[8:0]
Output
Logic
Reg.
9
18
9
BWS[0]
VREF
W
rite
Add.
De
code
9
LD
Control
20
1M
x
9
Array
1M
x
9
Arr
a
y
Write
Reg
Write
Reg
CQ
R/W
DOFF
QVLD
9