參數(shù)資料
型號: CY7C1161V18-333BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 2M X 8 QDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165
文件頁數(shù): 4/29頁
文件大小: 659K
代理商: CY7C1161V18-333BZC
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D
Page 12 of 29
The write cycle descriptions of CY7C1165V18 follows.[3, 11]
BWS0
BWS1
BWS2
BWS3
K
Comments
LLLL
L–H
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
LLLL
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
L–H
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
H
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
L
H
L–H
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
L–H
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
L
H
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
L
L–H
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
HHHH
L–H
No data is written into the device during this portion of a write operation.
HHHH
L–H No data is written into the device during this portion of a write operation.
相關(guān)PDF資料
PDF描述
CY7C1161V18-300BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1161V18-300BZXC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1161V18 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1168V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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