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參數(shù)資料
| 型號： | CY7C1170V18-300BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 512K X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 648K |
| 代理商： | CY7C1170V18-300BZXC |
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CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 21 of 27
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
5pF
CCLK
Clock Input Capacitance
6
pF
CO
Output Capacitance
7pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
165 FBGA
Package
Unit
Θ
JA
Thermal Resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
17.2
°C/W
Θ
JC
Thermal Resistance
(junction to case)
4.15
°C/W
AC Test Loads and Waveforms
Figure 6. AC Test loads and Waveforms
1.25V
0.25V
R = 50
Ω
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
DEVICE
RL = 50Ω
Z0 = 50Ω
VREF = 0.75V
[20]
0.75V
UNDER
TEST
0.75V
DEVICE
UNDER
TEST
OUTPUT
0.75V
VREF
OUTPUT
ZQ
(a)
SLEW RATE= 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
Note
20. Unless otherwise noted, test conditions are based on a signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1170V18-300BZXI | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1170V18-333BZC | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1170V18-333BZI | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1170V18-333BZXC | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1170V18-333BZXI | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1170V18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 18M DDRII+, B2, 2.5 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1170V18-400BZXC | 功能描述:靜態(tài)隨機存取存儲器 18M DDRII+, B2, 2.5 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1170XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100ACT | 制造商:Cypress Semiconductor 功能描述: |
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