參數(shù)資料
型號(hào): CY7C1170V18-333BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 12/27頁
文件大?。?/td> 648K
代理商: CY7C1170V18-333BZC
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 2 of 27
Logic Block Diagram (CY7C1166V18)
Logic Block Diagram (CY7C1177V18)
CLK
A(19:0)
Gen.
K
Control
Logic
Address
Register
Read
Add.
D
e
code
Read Data Reg.
R/W
DQ[7:0]
Output
Logic
Reg.
8
16
8
NWS[1:0]
VREF
W
rite
Add.
D
e
code
8
LD
Control
20
1M
x
8
Array
1M
x
8
Arr
a
y
Write
Reg
Write
Reg
CQ
R/W
DOFF
QVLD
8
CLK
A(19:0)
Gen.
K
Control
Logic
Address
Register
Read
Add.
De
code
Read Data Reg.
R/W
DQ[8:0]
Output
Logic
Reg.
9
18
9
BWS[0]
VREF
W
rite
Add.
De
code
9
LD
Control
20
1M
x
9
Array
1M
x
9
Arr
a
y
Write
Reg
Write
Reg
CQ
R/W
DOFF
QVLD
9
相關(guān)PDF資料
PDF描述
CY7C1170V18-333BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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參數(shù)描述
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CY7C1170V18-400BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18M DDRII+, B2, 2.5 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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