參數(shù)資料
型號: CY7C1170V18-333BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 7/27頁
文件大?。?/td> 648K
代理商: CY7C1170V18-333BZI
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 15 of 27
TAP Controller Block Diagram
Figure 3. Tap Controller Block Diagram
TAP Electrical Characteristics
The Tap Electrical Characteristics table over the operating range follows.[10, 11, 12]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = 2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = 100 μA1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA0.2
V
VIH
Input HIGH Voltage
0.65 VDD VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.35 VDD
V
IX
Input and Output Load Current
GND
≤ V
I ≤ VDD
55
μA
0
1
2
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
106
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
Notes
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
11. Overshoot: VIH(AC) < VDDQ + 0.35V (pulse width less than tCYC/2), undershoot: VIL(AC) > 0.3V (pulse width less than tCYC/2).
12. All voltage refer to ground.
相關(guān)PDF資料
PDF描述
CY7C1170V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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