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| 型號(hào)： | CY7C1177V18-333BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 2M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 15/27頁(yè) |
| 文件大?。?/td> | 648K |
| 代理商： | CY7C1177V18-333BZC |
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CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 22 of 27
Switching Characteristics
Cypress
Parameter
Consortium
Parameter
Description
400 MHz
375 MHz
333 MHz
300 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tPOWER
VDD(Typical) to the first Access
1–
1
–
1
–
1–
ms
tCYC
tKHKH
K Clock Cycle Time
2.50 8.40 2.66 8.40
3.0
8.40
3.3
8.40
ns
tKH
tKHKL
Input Clock (K/K) HIGH
0.4–0.4
–0.4–0.4
–
tCYC
tKL
tKLKH
Input Clock (K/K) LOW
0.4–0.4
–0.4–0.4
–
tCYC
tKHKH
K Clock Rise to K Clock Rise
(rising edge to rising edge)
1.06
–1.13–
1.28–1.40
–
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.4
–
0.4
–
0.4
–
0.4
–
ns
tSC
tIVKH
Control Setup to K Clock Rise (LD, R/W)
0.4–0.4
–0.4–0.4
–
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.28
–0.28–
0.28–0.28
–
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.28–
0.28
–0.28
–
0.28–
ns
Hold Times
tHA
tKHAX
Address Hold after K Clock Rise
0.4–0.4
–0.4–0.4
–
ns
tHC
tKHIX
Control Hold after K Clock Rise (LD, R/W)
0.4–0.4
–0.4–0.4
–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.28
–0.28–
0.28–0.28
–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.28
–0.28–
0.28–0.28
–
ns
Output Times
tCO
tCHQV
K/K Clock Rise to Data Valid
–
0.45
–
0.45
–
0.45
–
0.45
ns
tDOH
tCHQX
Data Output Hold after K/K Clock Rise
(Active to Active)
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
tCCQO
tCHCQV
K/K Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
ns
tCQOH
tCHCQX
Echo Clock Hold after K/K Clock Rise
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
–
0.2
–
0.2
–
0.2
–
0.2
ns
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.2
–
–0.2
–
–0.2
–
–0.2
–
ns
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH[23]
0.81
–0.88–
1.03–1.15
–
ns
tCQHCQH
CQ Clock Rise to CQ Clock Rise[23]
(rising edge to rising edge)
0.81
–0.88–
1.03–1.15
–
ns
tCHZ
tCHQZ
Clock (K/K) Rise to High-Z (Active to High-Z)[24, 25]
–
0.45–
0.45
–0.45–
0.45
ns
tCLZ
tCHQX1
Clock (K/K) Rise to Low-Z[24, 25]
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
tQVLD
Echo Clock High to QVLD Valid[26]
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20
ns
DLL Timing
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
–
0.20
ns
tKC lock
DLL Lock Time (K)
2048
–
2048
–
2048
–
2048
–
Cycles
tKC Reset
K Static to DLL Reset[27]
30–30–30–30–
ns
Notes
21. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
22. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be
initiated.
23. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.
24. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ± 100 mV from steady-state
voltage.
25. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
26. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
27. Hold to >VIH or <VIL.
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