參數(shù)資料
型號: CY7C1177V18-333BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 2M X 9 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 8/27頁
文件大?。?/td> 648K
代理商: CY7C1177V18-333BZI
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 16 of 27
TAP AC Switching Characteristics
The Tap AC Switching Characteristics over the operating range follows.[13, 14]
Parameter
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
50
ns
tTF
TCK Clock Frequency
20
MHz
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
ns
TAP Timing and Test Condition
The Tap Timing and Test Conditions for the CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 follows.[14]
Figure 4. TAP Timing and Test Conditions
tTL
tTH
(a)
TDO
CL = 20 pF
Z0 = 50Ω
GND
0.9V
50
Ω
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
tTCYC
tTMSH
tTMSS
tTDIS
tTDIH
tTDOV
tTDOX
TDO
Notes
13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns
相關(guān)PDF資料
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CY7C1177V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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