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參數(shù)資料
| 型號(hào)： | CY7C1338G-133BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
| 中文描述： | 128K X 32 CACHE SRAM, 6.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大小： | 291K |
| 代理商： | CY7C1338G-133BGI |
PRELIMINARY
CY7C1338G
Document #: 38-05521 Rev. *A
Page 5 of 17
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
[A:D]
)
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
[A:D]
will be
written into the specified address location. Byte writes are
allowed. During byte writes, BW
A
controls DQ
A
, BW
B
controls
DQ
B
, BW
C
controls DQ
C
, and BW
D
controls DQ
D
. All I/Os are
tri-stated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
Burst Sequences
The CY7C1338G provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
leaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
ZZREC
after the ZZ input returns
LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
Second
Address
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A
1
,
A
0
00
01
10
11
Second
Address
A
1
,
A
0
01
10
11
00
Third
Address
A
1
,
A
0
10
11
00
01
Fourth
Address
A
1
,
A
0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
Min.
Max.
40
2t
CYC
Unit
mA
ns
ns
ns
ns
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
2t
CYC
2t
CYC
0
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|---|---|
| CY7C1338S-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1338S-100AXC RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1338S-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 CY7C1338S-100AXCT RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1339-166AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1339A-100AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:4MB (128K X 32 )- BURST SYNCHROUNOUS PIPELINE SRAM - Bulk 制造商:Cypress Semiconductor 功能描述:128KX32 4M PIPELINE 3.3V CACHE 100.000 MHZ |
| CY7C1339A-100ACT | 制造商:Cypress Semiconductor 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel |
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