參數(shù)資料
型號(hào)： CY7C1338G-133BGXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 4-Mbit (128K x 32) Flow-Through Sync SRAM
中文描述： 128K X 32 CACHE SRAM, 6.5 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
文件頁(yè)數(shù)： 9/17頁(yè)
文件大?。?/td> 291K
代理商： CY7C1338G-133BGXC
PRELIMINARY
CY7C1338G
Document #: 38-05521 Rev. *A
Page 9 of 17
Thermal Resistance
[10]
Parameter
Θ
JA
Description
Test Conditions
TQFP Package
TBD
BGA Package
TBD
Unit
°C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA / JESD51.
Θ
JC
TBD
TBD
°C/W
Capacitance
[10]
Parameter
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
DD
= 3.3V. V
DDQ
= 3.3V
TQFP Package
5
BGA Package
5
Unit
pF
C
IN
Input Capacitance
C
CLK
C
I/O
Clock Input Capacitance
Input/Output Capacitance
5
5
5
7
pF
pF
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[11, 12, 13, 14, 15, 16]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
Shaded areas contain advance information.
Notes:
10.Tested initially and after any design or process change that may affect these parameters.
11. This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
12.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14.This parameter is sampled and not 100% tested.
15.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
16.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Description
133 MHz
Min.
1
117 MHz
Min.
1
100 MHz
Min.
1
Unit
ms
Max.
Max.
Max.
V
DD
(Typical) to the first Access
[11]
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
2.5
2.5
8.5
3.0
3.0
10
4.0
4.0
ns
ns
ns
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
6.5
7.5
8.0
ns
ns
2.0
2.0
2.0
OUTPUT
R = 317
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.5V
3.3V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤
1ns
≤
1ns
(c)
OUTPUT
R = 1667
R =1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.25V
2.5V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤
1ns
≤
1ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
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