參數(shù)資料
型號(hào)： CY7C1347G
廠商： Cypress Semiconductor Corp.
英文描述： 4-Mbit (128K x 36) Pipelined Sync SRAM
中文描述： 4兆位（128K的× 36）流水線同步靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù)： 12/21頁(yè)
文件大?。?/td> 841K
代理商： CY7C1347G
CY7C1347G
Document #: 38-05516 Rev. *E
Page 12 of 21
Switching Characteristics
Over the Operating Range
[14, 15]
Parameter
Description
–250
–200
–166
–133
Unit
Min
Max
Min
Max
Min
Max
Min
Max
t
POWER
Clock
V
DD
(Typical) to the first Access
[10]
1
1
1
1
ms
t
CYC
t
CH
t
CL
Output Times
Clock Cycle Time
4.0
5.0
6.0
7.5
ns
Clock HIGH
1.7
2.0
2.5
3.0
ns
Clock LOW
1.7
2.0
2.5
3.0
ns
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
Data Output Valid After CLK Rise
2.6
2.8
3.5
4.0
ns
Data Output Hold After CLK Rise
Clock to Low-Z
[11, 12, 13]
Clock to High-Z
[11, 12, 13]
1.0
1.0
1.5
1.5
ns
0
0
0
0
ns
2.6
2.8
3.5
4.0
ns
OE LOW to Output Valid
OE LOW to Output Low-Z
[11, 12, 13]
OE HIGH to Output High-Z
[11, 12, 13]
2.6
2.8
3.5
4.5
ns
0
0
0
0
ns
2.6
2.8
3.5
4.0
ns
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
Address Setup Before CLK Rise
1.2
1.2
1.5
1.5
ns
ADSC, ADSP Setup Before CLK Rise
1.2
1.2
1.5
1.5
ns
ADV Setup Before CLK Rise
1.2
1.2
1.5
1.5
ns
GW, BWE, BW
X
Setup Before CLK Rise
Data Input Setup Before CLK Rise
1.2
1.2
1.5
1.5
ns
1.2
1.2
1.5
1.5
ns
Chip Enable Setup Before CLK Rise
1.2
1.2
1.5
1.5
ns
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Address Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
ADSP, ADSC Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
ADV Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
GW, BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
0.3
0.5
0.5
0.5
ns
Chip Enable Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
Notes
10.This part has an internal voltage regulator; t
POWER
is the time that the power must be supplied above V
DD
(min) initially before a read or write operation can be
initiated.
11. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of
“AC Test Loads and Waveforms” on page 11
. Transition is measured ±200 mV
from steady-state voltage.
12.At any voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z prior to Low-Z under the same system conditions.
13.This parameter is sampled and not 100% tested.
14.Timing references level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V on all data sheets.
15.Test conditions shown in (a) of
“AC Test Loads and Waveforms” on page 11
unless otherwise noted.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1347G-100AXC 功能描述:IC SRAM 4.5MBIT 100MHZ 100LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱(chēng):557-1327-2
CY7C1347G-133AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1347G-133AXC 制造商:Cypress Semiconductor 功能描述:IC SRAM 4MBIT PARALLEL 4NS TQFP-100
CY7C1347G-133AXCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1347G-133AXI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 128Kx36 3.3V IND Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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